platform.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511
  1. /*
  2. * platform.c - DesignWare HS OTG Controller platform driver
  3. *
  4. * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions
  8. * are met:
  9. * 1. Redistributions of source code must retain the above copyright
  10. * notice, this list of conditions, and the following disclaimer,
  11. * without modification.
  12. * 2. Redistributions in binary form must reproduce the above copyright
  13. * notice, this list of conditions and the following disclaimer in the
  14. * documentation and/or other materials provided with the distribution.
  15. * 3. The names of the above-listed copyright holders may not be used
  16. * to endorse or promote products derived from this software without
  17. * specific prior written permission.
  18. *
  19. * ALTERNATIVELY, this software may be distributed under the terms of the
  20. * GNU General Public License ("GPL") as published by the Free Software
  21. * Foundation; either version 2 of the License, or (at your option) any
  22. * later version.
  23. *
  24. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35. */
  36. #include <linux/kernel.h>
  37. #include <linux/module.h>
  38. #include <linux/slab.h>
  39. #include <linux/clk.h>
  40. #include <linux/device.h>
  41. #include <linux/dma-mapping.h>
  42. #include <linux/of_device.h>
  43. #include <linux/mutex.h>
  44. #include <linux/platform_device.h>
  45. #include <linux/phy/phy.h>
  46. #include <linux/platform_data/s3c-hsotg.h>
  47. #include <linux/usb/of.h>
  48. #include "core.h"
  49. #include "hcd.h"
  50. #include "debug.h"
  51. static const char dwc2_driver_name[] = "dwc2";
  52. static const struct dwc2_core_params params_bcm2835 = {
  53. .otg_cap = 0, /* HNP/SRP capable */
  54. .otg_ver = 0, /* 1.3 */
  55. .dma_enable = 1,
  56. .dma_desc_enable = 0,
  57. .speed = 0, /* High Speed */
  58. .enable_dynamic_fifo = 1,
  59. .en_multiple_tx_fifo = 1,
  60. .host_rx_fifo_size = 774, /* 774 DWORDs */
  61. .host_nperio_tx_fifo_size = 256, /* 256 DWORDs */
  62. .host_perio_tx_fifo_size = 512, /* 512 DWORDs */
  63. .max_transfer_size = 65535,
  64. .max_packet_count = 511,
  65. .host_channels = 8,
  66. .phy_type = 1, /* UTMI */
  67. .phy_utmi_width = 8, /* 8 bits */
  68. .phy_ulpi_ddr = 0, /* Single */
  69. .phy_ulpi_ext_vbus = 0,
  70. .i2c_enable = 0,
  71. .ulpi_fs_ls = 0,
  72. .host_support_fs_ls_low_power = 0,
  73. .host_ls_low_power_phy_clk = 0, /* 48 MHz */
  74. .ts_dline = 0,
  75. .reload_ctl = 0,
  76. .ahbcfg = 0x10,
  77. .uframe_sched = 0,
  78. .external_id_pin_ctl = -1,
  79. .hibernation = -1,
  80. };
  81. static const struct dwc2_core_params params_rk3066 = {
  82. .otg_cap = 2, /* non-HNP/non-SRP */
  83. .otg_ver = -1,
  84. .dma_enable = -1,
  85. .dma_desc_enable = 0,
  86. .speed = -1,
  87. .enable_dynamic_fifo = 1,
  88. .en_multiple_tx_fifo = -1,
  89. .host_rx_fifo_size = 520, /* 520 DWORDs */
  90. .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
  91. .host_perio_tx_fifo_size = 256, /* 256 DWORDs */
  92. .max_transfer_size = 65535,
  93. .max_packet_count = -1,
  94. .host_channels = -1,
  95. .phy_type = -1,
  96. .phy_utmi_width = -1,
  97. .phy_ulpi_ddr = -1,
  98. .phy_ulpi_ext_vbus = -1,
  99. .i2c_enable = -1,
  100. .ulpi_fs_ls = -1,
  101. .host_support_fs_ls_low_power = -1,
  102. .host_ls_low_power_phy_clk = -1,
  103. .ts_dline = -1,
  104. .reload_ctl = -1,
  105. .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  106. GAHBCFG_HBSTLEN_SHIFT,
  107. .uframe_sched = -1,
  108. .external_id_pin_ctl = -1,
  109. .hibernation = -1,
  110. };
  111. static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
  112. {
  113. struct platform_device *pdev = to_platform_device(hsotg->dev);
  114. int ret;
  115. ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
  116. hsotg->supplies);
  117. if (ret)
  118. return ret;
  119. if (hsotg->clk) {
  120. ret = clk_prepare_enable(hsotg->clk);
  121. if (ret)
  122. return ret;
  123. }
  124. if (hsotg->uphy)
  125. ret = usb_phy_init(hsotg->uphy);
  126. else if (hsotg->plat && hsotg->plat->phy_init)
  127. ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
  128. else {
  129. ret = phy_power_on(hsotg->phy);
  130. if (ret == 0)
  131. ret = phy_init(hsotg->phy);
  132. }
  133. return ret;
  134. }
  135. /**
  136. * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
  137. * @hsotg: The driver state
  138. *
  139. * A wrapper for platform code responsible for controlling
  140. * low-level USB platform resources (phy, clock, regulators)
  141. */
  142. int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
  143. {
  144. int ret = __dwc2_lowlevel_hw_enable(hsotg);
  145. if (ret == 0)
  146. hsotg->ll_hw_enabled = true;
  147. return ret;
  148. }
  149. static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
  150. {
  151. struct platform_device *pdev = to_platform_device(hsotg->dev);
  152. int ret = 0;
  153. if (hsotg->uphy)
  154. usb_phy_shutdown(hsotg->uphy);
  155. else if (hsotg->plat && hsotg->plat->phy_exit)
  156. ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
  157. else {
  158. ret = phy_exit(hsotg->phy);
  159. if (ret == 0)
  160. ret = phy_power_off(hsotg->phy);
  161. }
  162. if (ret)
  163. return ret;
  164. if (hsotg->clk)
  165. clk_disable_unprepare(hsotg->clk);
  166. ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
  167. hsotg->supplies);
  168. return ret;
  169. }
  170. /**
  171. * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
  172. * @hsotg: The driver state
  173. *
  174. * A wrapper for platform code responsible for controlling
  175. * low-level USB platform resources (phy, clock, regulators)
  176. */
  177. int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
  178. {
  179. int ret = __dwc2_lowlevel_hw_disable(hsotg);
  180. if (ret == 0)
  181. hsotg->ll_hw_enabled = false;
  182. return ret;
  183. }
  184. static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
  185. {
  186. int i, ret;
  187. /* Set default UTMI width */
  188. hsotg->phyif = GUSBCFG_PHYIF16;
  189. /*
  190. * Attempt to find a generic PHY, then look for an old style
  191. * USB PHY and then fall back to pdata
  192. */
  193. hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
  194. if (IS_ERR(hsotg->phy)) {
  195. ret = PTR_ERR(hsotg->phy);
  196. switch (ret) {
  197. case -ENODEV:
  198. case -ENOSYS:
  199. hsotg->phy = NULL;
  200. break;
  201. case -EPROBE_DEFER:
  202. return ret;
  203. default:
  204. dev_err(hsotg->dev, "error getting phy %d\n", ret);
  205. return ret;
  206. }
  207. }
  208. if (!hsotg->phy) {
  209. hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
  210. if (IS_ERR(hsotg->uphy)) {
  211. ret = PTR_ERR(hsotg->uphy);
  212. switch (ret) {
  213. case -ENODEV:
  214. case -ENXIO:
  215. hsotg->uphy = NULL;
  216. break;
  217. case -EPROBE_DEFER:
  218. return ret;
  219. default:
  220. dev_err(hsotg->dev, "error getting usb phy %d\n",
  221. ret);
  222. return ret;
  223. }
  224. }
  225. }
  226. hsotg->plat = dev_get_platdata(hsotg->dev);
  227. if (hsotg->phy) {
  228. /*
  229. * If using the generic PHY framework, check if the PHY bus
  230. * width is 8-bit and set the phyif appropriately.
  231. */
  232. if (phy_get_bus_width(hsotg->phy) == 8)
  233. hsotg->phyif = GUSBCFG_PHYIF8;
  234. }
  235. /* Clock */
  236. hsotg->clk = devm_clk_get(hsotg->dev, "otg");
  237. if (IS_ERR(hsotg->clk)) {
  238. hsotg->clk = NULL;
  239. dev_dbg(hsotg->dev, "cannot get otg clock\n");
  240. }
  241. /* Regulators */
  242. for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
  243. hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
  244. ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
  245. hsotg->supplies);
  246. if (ret) {
  247. dev_err(hsotg->dev, "failed to request supplies: %d\n", ret);
  248. return ret;
  249. }
  250. return 0;
  251. }
  252. /**
  253. * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
  254. * DWC_otg driver
  255. *
  256. * @dev: Platform device
  257. *
  258. * This routine is called, for example, when the rmmod command is executed. The
  259. * device may or may not be electrically present. If it is present, the driver
  260. * stops device processing. Any resources used on behalf of this device are
  261. * freed.
  262. */
  263. static int dwc2_driver_remove(struct platform_device *dev)
  264. {
  265. struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
  266. dwc2_debugfs_exit(hsotg);
  267. if (hsotg->hcd_enabled)
  268. dwc2_hcd_remove(hsotg);
  269. if (hsotg->gadget_enabled)
  270. dwc2_hsotg_remove(hsotg);
  271. if (hsotg->ll_hw_enabled)
  272. dwc2_lowlevel_hw_disable(hsotg);
  273. return 0;
  274. }
  275. static const struct of_device_id dwc2_of_match_table[] = {
  276. { .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
  277. { .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
  278. { .compatible = "snps,dwc2", .data = NULL },
  279. { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
  280. {},
  281. };
  282. MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
  283. /**
  284. * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
  285. * driver
  286. *
  287. * @dev: Platform device
  288. *
  289. * This routine creates the driver components required to control the device
  290. * (core, HCD, and PCD) and initializes the device. The driver components are
  291. * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
  292. * in the device private data. This allows the driver to access the dwc2_hsotg
  293. * structure on subsequent calls to driver methods for this device.
  294. */
  295. static int dwc2_driver_probe(struct platform_device *dev)
  296. {
  297. const struct of_device_id *match;
  298. const struct dwc2_core_params *params;
  299. struct dwc2_core_params defparams;
  300. struct dwc2_hsotg *hsotg;
  301. struct resource *res;
  302. int retval;
  303. int irq;
  304. match = of_match_device(dwc2_of_match_table, &dev->dev);
  305. if (match && match->data) {
  306. params = match->data;
  307. } else {
  308. /* Default all params to autodetect */
  309. dwc2_set_all_params(&defparams, -1);
  310. params = &defparams;
  311. /*
  312. * Disable descriptor dma mode by default as the HW can support
  313. * it, but does not support it for SPLIT transactions.
  314. */
  315. defparams.dma_desc_enable = 0;
  316. }
  317. hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
  318. if (!hsotg)
  319. return -ENOMEM;
  320. hsotg->dev = &dev->dev;
  321. /*
  322. * Use reasonable defaults so platforms don't have to provide these.
  323. */
  324. if (!dev->dev.dma_mask)
  325. dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
  326. retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
  327. if (retval)
  328. return retval;
  329. res = platform_get_resource(dev, IORESOURCE_MEM, 0);
  330. hsotg->regs = devm_ioremap_resource(&dev->dev, res);
  331. if (IS_ERR(hsotg->regs))
  332. return PTR_ERR(hsotg->regs);
  333. dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
  334. (unsigned long)res->start, hsotg->regs);
  335. hsotg->dr_mode = usb_get_dr_mode(&dev->dev);
  336. if (IS_ENABLED(CONFIG_USB_DWC2_HOST) &&
  337. hsotg->dr_mode != USB_DR_MODE_HOST) {
  338. hsotg->dr_mode = USB_DR_MODE_HOST;
  339. dev_warn(hsotg->dev,
  340. "Configuration mismatch. Forcing host mode\n");
  341. } else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) &&
  342. hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
  343. hsotg->dr_mode = USB_DR_MODE_PERIPHERAL;
  344. dev_warn(hsotg->dev,
  345. "Configuration mismatch. Forcing peripheral mode\n");
  346. }
  347. retval = dwc2_lowlevel_hw_init(hsotg);
  348. if (retval)
  349. return retval;
  350. spin_lock_init(&hsotg->lock);
  351. hsotg->core_params = devm_kzalloc(&dev->dev,
  352. sizeof(*hsotg->core_params), GFP_KERNEL);
  353. if (!hsotg->core_params)
  354. return -ENOMEM;
  355. dwc2_set_all_params(hsotg->core_params, -1);
  356. irq = platform_get_irq(dev, 0);
  357. if (irq < 0) {
  358. dev_err(&dev->dev, "missing IRQ resource\n");
  359. return irq;
  360. }
  361. dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
  362. irq);
  363. retval = devm_request_irq(hsotg->dev, irq,
  364. dwc2_handle_common_intr, IRQF_SHARED,
  365. dev_name(hsotg->dev), hsotg);
  366. if (retval)
  367. return retval;
  368. retval = dwc2_lowlevel_hw_enable(hsotg);
  369. if (retval)
  370. return retval;
  371. /* Detect config values from hardware */
  372. retval = dwc2_get_hwparams(hsotg);
  373. if (retval)
  374. goto error;
  375. /* Validate parameter values */
  376. dwc2_set_parameters(hsotg, params);
  377. if (hsotg->dr_mode != USB_DR_MODE_HOST) {
  378. retval = dwc2_gadget_init(hsotg, irq);
  379. if (retval)
  380. goto error;
  381. hsotg->gadget_enabled = 1;
  382. }
  383. if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
  384. retval = dwc2_hcd_init(hsotg, irq);
  385. if (retval) {
  386. if (hsotg->gadget_enabled)
  387. dwc2_hsotg_remove(hsotg);
  388. goto error;
  389. }
  390. hsotg->hcd_enabled = 1;
  391. }
  392. platform_set_drvdata(dev, hsotg);
  393. dwc2_debugfs_init(hsotg);
  394. /* Gadget code manages lowlevel hw on its own */
  395. if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
  396. dwc2_lowlevel_hw_disable(hsotg);
  397. return 0;
  398. error:
  399. dwc2_lowlevel_hw_disable(hsotg);
  400. return retval;
  401. }
  402. static int __maybe_unused dwc2_suspend(struct device *dev)
  403. {
  404. struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
  405. int ret = 0;
  406. if (dwc2_is_device_mode(dwc2))
  407. dwc2_hsotg_suspend(dwc2);
  408. if (dwc2->ll_hw_enabled)
  409. ret = __dwc2_lowlevel_hw_disable(dwc2);
  410. return ret;
  411. }
  412. static int __maybe_unused dwc2_resume(struct device *dev)
  413. {
  414. struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
  415. int ret = 0;
  416. if (dwc2->ll_hw_enabled) {
  417. ret = __dwc2_lowlevel_hw_enable(dwc2);
  418. if (ret)
  419. return ret;
  420. }
  421. if (dwc2_is_device_mode(dwc2))
  422. ret = dwc2_hsotg_resume(dwc2);
  423. return ret;
  424. }
  425. static const struct dev_pm_ops dwc2_dev_pm_ops = {
  426. SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
  427. };
  428. static struct platform_driver dwc2_platform_driver = {
  429. .driver = {
  430. .name = dwc2_driver_name,
  431. .of_match_table = dwc2_of_match_table,
  432. .pm = &dwc2_dev_pm_ops,
  433. },
  434. .probe = dwc2_driver_probe,
  435. .remove = dwc2_driver_remove,
  436. };
  437. module_platform_driver(dwc2_platform_driver);
  438. MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
  439. MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
  440. MODULE_LICENSE("Dual BSD/GPL");