fotg210-udc.c 29 KB

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  1. /*
  2. * FOTG210 UDC Driver supports Bulk transfer so far
  3. *
  4. * Copyright (C) 2013 Faraday Technology Corporation
  5. *
  6. * Author : Yuan-Hsin Chen <yhchen@faraday-tech.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. */
  12. #include <linux/dma-mapping.h>
  13. #include <linux/err.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/module.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/usb/ch9.h>
  19. #include <linux/usb/gadget.h>
  20. #include "fotg210.h"
  21. #define DRIVER_DESC "FOTG210 USB Device Controller Driver"
  22. #define DRIVER_VERSION "30-April-2013"
  23. static const char udc_name[] = "fotg210_udc";
  24. static const char * const fotg210_ep_name[] = {
  25. "ep0", "ep1", "ep2", "ep3", "ep4"};
  26. static void fotg210_disable_fifo_int(struct fotg210_ep *ep)
  27. {
  28. u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
  29. if (ep->dir_in)
  30. value |= DMISGR1_MF_IN_INT(ep->epnum - 1);
  31. else
  32. value |= DMISGR1_MF_OUTSPK_INT(ep->epnum - 1);
  33. iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1);
  34. }
  35. static void fotg210_enable_fifo_int(struct fotg210_ep *ep)
  36. {
  37. u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1);
  38. if (ep->dir_in)
  39. value &= ~DMISGR1_MF_IN_INT(ep->epnum - 1);
  40. else
  41. value &= ~DMISGR1_MF_OUTSPK_INT(ep->epnum - 1);
  42. iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1);
  43. }
  44. static void fotg210_set_cxdone(struct fotg210_udc *fotg210)
  45. {
  46. u32 value = ioread32(fotg210->reg + FOTG210_DCFESR);
  47. value |= DCFESR_CX_DONE;
  48. iowrite32(value, fotg210->reg + FOTG210_DCFESR);
  49. }
  50. static void fotg210_done(struct fotg210_ep *ep, struct fotg210_request *req,
  51. int status)
  52. {
  53. list_del_init(&req->queue);
  54. /* don't modify queue heads during completion callback */
  55. if (ep->fotg210->gadget.speed == USB_SPEED_UNKNOWN)
  56. req->req.status = -ESHUTDOWN;
  57. else
  58. req->req.status = status;
  59. spin_unlock(&ep->fotg210->lock);
  60. usb_gadget_giveback_request(&ep->ep, &req->req);
  61. spin_lock(&ep->fotg210->lock);
  62. if (ep->epnum) {
  63. if (list_empty(&ep->queue))
  64. fotg210_disable_fifo_int(ep);
  65. } else {
  66. fotg210_set_cxdone(ep->fotg210);
  67. }
  68. }
  69. static void fotg210_fifo_ep_mapping(struct fotg210_ep *ep, u32 epnum,
  70. u32 dir_in)
  71. {
  72. struct fotg210_udc *fotg210 = ep->fotg210;
  73. u32 val;
  74. /* Driver should map an ep to a fifo and then map the fifo
  75. * to the ep. What a brain-damaged design!
  76. */
  77. /* map a fifo to an ep */
  78. val = ioread32(fotg210->reg + FOTG210_EPMAP);
  79. val &= ~EPMAP_FIFONOMSK(epnum, dir_in);
  80. val |= EPMAP_FIFONO(epnum, dir_in);
  81. iowrite32(val, fotg210->reg + FOTG210_EPMAP);
  82. /* map the ep to the fifo */
  83. val = ioread32(fotg210->reg + FOTG210_FIFOMAP);
  84. val &= ~FIFOMAP_EPNOMSK(epnum);
  85. val |= FIFOMAP_EPNO(epnum);
  86. iowrite32(val, fotg210->reg + FOTG210_FIFOMAP);
  87. /* enable fifo */
  88. val = ioread32(fotg210->reg + FOTG210_FIFOCF);
  89. val |= FIFOCF_FIFO_EN(epnum - 1);
  90. iowrite32(val, fotg210->reg + FOTG210_FIFOCF);
  91. }
  92. static void fotg210_set_fifo_dir(struct fotg210_ep *ep, u32 epnum, u32 dir_in)
  93. {
  94. struct fotg210_udc *fotg210 = ep->fotg210;
  95. u32 val;
  96. val = ioread32(fotg210->reg + FOTG210_FIFOMAP);
  97. val |= (dir_in ? FIFOMAP_DIRIN(epnum - 1) : FIFOMAP_DIROUT(epnum - 1));
  98. iowrite32(val, fotg210->reg + FOTG210_FIFOMAP);
  99. }
  100. static void fotg210_set_tfrtype(struct fotg210_ep *ep, u32 epnum, u32 type)
  101. {
  102. struct fotg210_udc *fotg210 = ep->fotg210;
  103. u32 val;
  104. val = ioread32(fotg210->reg + FOTG210_FIFOCF);
  105. val |= FIFOCF_TYPE(type, epnum - 1);
  106. iowrite32(val, fotg210->reg + FOTG210_FIFOCF);
  107. }
  108. static void fotg210_set_mps(struct fotg210_ep *ep, u32 epnum, u32 mps,
  109. u32 dir_in)
  110. {
  111. struct fotg210_udc *fotg210 = ep->fotg210;
  112. u32 val;
  113. u32 offset = dir_in ? FOTG210_INEPMPSR(epnum) :
  114. FOTG210_OUTEPMPSR(epnum);
  115. val = ioread32(fotg210->reg + offset);
  116. val |= INOUTEPMPSR_MPS(mps);
  117. iowrite32(val, fotg210->reg + offset);
  118. }
  119. static int fotg210_config_ep(struct fotg210_ep *ep,
  120. const struct usb_endpoint_descriptor *desc)
  121. {
  122. struct fotg210_udc *fotg210 = ep->fotg210;
  123. fotg210_set_fifo_dir(ep, ep->epnum, ep->dir_in);
  124. fotg210_set_tfrtype(ep, ep->epnum, ep->type);
  125. fotg210_set_mps(ep, ep->epnum, ep->ep.maxpacket, ep->dir_in);
  126. fotg210_fifo_ep_mapping(ep, ep->epnum, ep->dir_in);
  127. fotg210->ep[ep->epnum] = ep;
  128. return 0;
  129. }
  130. static int fotg210_ep_enable(struct usb_ep *_ep,
  131. const struct usb_endpoint_descriptor *desc)
  132. {
  133. struct fotg210_ep *ep;
  134. ep = container_of(_ep, struct fotg210_ep, ep);
  135. ep->desc = desc;
  136. ep->epnum = usb_endpoint_num(desc);
  137. ep->type = usb_endpoint_type(desc);
  138. ep->dir_in = usb_endpoint_dir_in(desc);
  139. ep->ep.maxpacket = usb_endpoint_maxp(desc);
  140. return fotg210_config_ep(ep, desc);
  141. }
  142. static void fotg210_reset_tseq(struct fotg210_udc *fotg210, u8 epnum)
  143. {
  144. struct fotg210_ep *ep = fotg210->ep[epnum];
  145. u32 value;
  146. void __iomem *reg;
  147. reg = (ep->dir_in) ?
  148. fotg210->reg + FOTG210_INEPMPSR(epnum) :
  149. fotg210->reg + FOTG210_OUTEPMPSR(epnum);
  150. /* Note: Driver needs to set and clear INOUTEPMPSR_RESET_TSEQ
  151. * bit. Controller wouldn't clear this bit. WTF!!!
  152. */
  153. value = ioread32(reg);
  154. value |= INOUTEPMPSR_RESET_TSEQ;
  155. iowrite32(value, reg);
  156. value = ioread32(reg);
  157. value &= ~INOUTEPMPSR_RESET_TSEQ;
  158. iowrite32(value, reg);
  159. }
  160. static int fotg210_ep_release(struct fotg210_ep *ep)
  161. {
  162. if (!ep->epnum)
  163. return 0;
  164. ep->epnum = 0;
  165. ep->stall = 0;
  166. ep->wedged = 0;
  167. fotg210_reset_tseq(ep->fotg210, ep->epnum);
  168. return 0;
  169. }
  170. static int fotg210_ep_disable(struct usb_ep *_ep)
  171. {
  172. struct fotg210_ep *ep;
  173. struct fotg210_request *req;
  174. unsigned long flags;
  175. BUG_ON(!_ep);
  176. ep = container_of(_ep, struct fotg210_ep, ep);
  177. while (!list_empty(&ep->queue)) {
  178. req = list_entry(ep->queue.next,
  179. struct fotg210_request, queue);
  180. spin_lock_irqsave(&ep->fotg210->lock, flags);
  181. fotg210_done(ep, req, -ECONNRESET);
  182. spin_unlock_irqrestore(&ep->fotg210->lock, flags);
  183. }
  184. return fotg210_ep_release(ep);
  185. }
  186. static struct usb_request *fotg210_ep_alloc_request(struct usb_ep *_ep,
  187. gfp_t gfp_flags)
  188. {
  189. struct fotg210_request *req;
  190. req = kzalloc(sizeof(struct fotg210_request), gfp_flags);
  191. if (!req)
  192. return NULL;
  193. INIT_LIST_HEAD(&req->queue);
  194. return &req->req;
  195. }
  196. static void fotg210_ep_free_request(struct usb_ep *_ep,
  197. struct usb_request *_req)
  198. {
  199. struct fotg210_request *req;
  200. req = container_of(_req, struct fotg210_request, req);
  201. kfree(req);
  202. }
  203. static void fotg210_enable_dma(struct fotg210_ep *ep,
  204. dma_addr_t d, u32 len)
  205. {
  206. u32 value;
  207. struct fotg210_udc *fotg210 = ep->fotg210;
  208. /* set transfer length and direction */
  209. value = ioread32(fotg210->reg + FOTG210_DMACPSR1);
  210. value &= ~(DMACPSR1_DMA_LEN(0xFFFF) | DMACPSR1_DMA_TYPE(1));
  211. value |= DMACPSR1_DMA_LEN(len) | DMACPSR1_DMA_TYPE(ep->dir_in);
  212. iowrite32(value, fotg210->reg + FOTG210_DMACPSR1);
  213. /* set device DMA target FIFO number */
  214. value = ioread32(fotg210->reg + FOTG210_DMATFNR);
  215. if (ep->epnum)
  216. value |= DMATFNR_ACC_FN(ep->epnum - 1);
  217. else
  218. value |= DMATFNR_ACC_CXF;
  219. iowrite32(value, fotg210->reg + FOTG210_DMATFNR);
  220. /* set DMA memory address */
  221. iowrite32(d, fotg210->reg + FOTG210_DMACPSR2);
  222. /* enable MDMA_EROR and MDMA_CMPLT interrupt */
  223. value = ioread32(fotg210->reg + FOTG210_DMISGR2);
  224. value &= ~(DMISGR2_MDMA_CMPLT | DMISGR2_MDMA_ERROR);
  225. iowrite32(value, fotg210->reg + FOTG210_DMISGR2);
  226. /* start DMA */
  227. value = ioread32(fotg210->reg + FOTG210_DMACPSR1);
  228. value |= DMACPSR1_DMA_START;
  229. iowrite32(value, fotg210->reg + FOTG210_DMACPSR1);
  230. }
  231. static void fotg210_disable_dma(struct fotg210_ep *ep)
  232. {
  233. iowrite32(DMATFNR_DISDMA, ep->fotg210->reg + FOTG210_DMATFNR);
  234. }
  235. static void fotg210_wait_dma_done(struct fotg210_ep *ep)
  236. {
  237. u32 value;
  238. do {
  239. value = ioread32(ep->fotg210->reg + FOTG210_DISGR2);
  240. if ((value & DISGR2_USBRST_INT) ||
  241. (value & DISGR2_DMA_ERROR))
  242. goto dma_reset;
  243. } while (!(value & DISGR2_DMA_CMPLT));
  244. value &= ~DISGR2_DMA_CMPLT;
  245. iowrite32(value, ep->fotg210->reg + FOTG210_DISGR2);
  246. return;
  247. dma_reset:
  248. value = ioread32(ep->fotg210->reg + FOTG210_DMACPSR1);
  249. value |= DMACPSR1_DMA_ABORT;
  250. iowrite32(value, ep->fotg210->reg + FOTG210_DMACPSR1);
  251. /* reset fifo */
  252. if (ep->epnum) {
  253. value = ioread32(ep->fotg210->reg +
  254. FOTG210_FIBCR(ep->epnum - 1));
  255. value |= FIBCR_FFRST;
  256. iowrite32(value, ep->fotg210->reg +
  257. FOTG210_FIBCR(ep->epnum - 1));
  258. } else {
  259. value = ioread32(ep->fotg210->reg + FOTG210_DCFESR);
  260. value |= DCFESR_CX_CLR;
  261. iowrite32(value, ep->fotg210->reg + FOTG210_DCFESR);
  262. }
  263. }
  264. static void fotg210_start_dma(struct fotg210_ep *ep,
  265. struct fotg210_request *req)
  266. {
  267. dma_addr_t d;
  268. u8 *buffer;
  269. u32 length;
  270. if (ep->epnum) {
  271. if (ep->dir_in) {
  272. buffer = req->req.buf;
  273. length = req->req.length;
  274. } else {
  275. buffer = req->req.buf + req->req.actual;
  276. length = ioread32(ep->fotg210->reg +
  277. FOTG210_FIBCR(ep->epnum - 1));
  278. length &= FIBCR_BCFX;
  279. }
  280. } else {
  281. buffer = req->req.buf + req->req.actual;
  282. if (req->req.length - req->req.actual > ep->ep.maxpacket)
  283. length = ep->ep.maxpacket;
  284. else
  285. length = req->req.length;
  286. }
  287. d = dma_map_single(NULL, buffer, length,
  288. ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  289. if (dma_mapping_error(NULL, d)) {
  290. pr_err("dma_mapping_error\n");
  291. return;
  292. }
  293. dma_sync_single_for_device(NULL, d, length,
  294. ep->dir_in ? DMA_TO_DEVICE :
  295. DMA_FROM_DEVICE);
  296. fotg210_enable_dma(ep, d, length);
  297. /* check if dma is done */
  298. fotg210_wait_dma_done(ep);
  299. fotg210_disable_dma(ep);
  300. /* update actual transfer length */
  301. req->req.actual += length;
  302. dma_unmap_single(NULL, d, length, DMA_TO_DEVICE);
  303. }
  304. static void fotg210_ep0_queue(struct fotg210_ep *ep,
  305. struct fotg210_request *req)
  306. {
  307. if (!req->req.length) {
  308. fotg210_done(ep, req, 0);
  309. return;
  310. }
  311. if (ep->dir_in) { /* if IN */
  312. fotg210_start_dma(ep, req);
  313. if ((req->req.length == req->req.actual) ||
  314. (req->req.actual < ep->ep.maxpacket))
  315. fotg210_done(ep, req, 0);
  316. } else { /* OUT */
  317. u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR0);
  318. value &= ~DMISGR0_MCX_OUT_INT;
  319. iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR0);
  320. }
  321. }
  322. static int fotg210_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
  323. gfp_t gfp_flags)
  324. {
  325. struct fotg210_ep *ep;
  326. struct fotg210_request *req;
  327. unsigned long flags;
  328. int request = 0;
  329. ep = container_of(_ep, struct fotg210_ep, ep);
  330. req = container_of(_req, struct fotg210_request, req);
  331. if (ep->fotg210->gadget.speed == USB_SPEED_UNKNOWN)
  332. return -ESHUTDOWN;
  333. spin_lock_irqsave(&ep->fotg210->lock, flags);
  334. if (list_empty(&ep->queue))
  335. request = 1;
  336. list_add_tail(&req->queue, &ep->queue);
  337. req->req.actual = 0;
  338. req->req.status = -EINPROGRESS;
  339. if (!ep->epnum) /* ep0 */
  340. fotg210_ep0_queue(ep, req);
  341. else if (request && !ep->stall)
  342. fotg210_enable_fifo_int(ep);
  343. spin_unlock_irqrestore(&ep->fotg210->lock, flags);
  344. return 0;
  345. }
  346. static int fotg210_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  347. {
  348. struct fotg210_ep *ep;
  349. struct fotg210_request *req;
  350. unsigned long flags;
  351. ep = container_of(_ep, struct fotg210_ep, ep);
  352. req = container_of(_req, struct fotg210_request, req);
  353. spin_lock_irqsave(&ep->fotg210->lock, flags);
  354. if (!list_empty(&ep->queue))
  355. fotg210_done(ep, req, -ECONNRESET);
  356. spin_unlock_irqrestore(&ep->fotg210->lock, flags);
  357. return 0;
  358. }
  359. static void fotg210_set_epnstall(struct fotg210_ep *ep)
  360. {
  361. struct fotg210_udc *fotg210 = ep->fotg210;
  362. u32 value;
  363. void __iomem *reg;
  364. /* check if IN FIFO is empty before stall */
  365. if (ep->dir_in) {
  366. do {
  367. value = ioread32(fotg210->reg + FOTG210_DCFESR);
  368. } while (!(value & DCFESR_FIFO_EMPTY(ep->epnum - 1)));
  369. }
  370. reg = (ep->dir_in) ?
  371. fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
  372. fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
  373. value = ioread32(reg);
  374. value |= INOUTEPMPSR_STL_EP;
  375. iowrite32(value, reg);
  376. }
  377. static void fotg210_clear_epnstall(struct fotg210_ep *ep)
  378. {
  379. struct fotg210_udc *fotg210 = ep->fotg210;
  380. u32 value;
  381. void __iomem *reg;
  382. reg = (ep->dir_in) ?
  383. fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
  384. fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
  385. value = ioread32(reg);
  386. value &= ~INOUTEPMPSR_STL_EP;
  387. iowrite32(value, reg);
  388. }
  389. static int fotg210_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge)
  390. {
  391. struct fotg210_ep *ep;
  392. struct fotg210_udc *fotg210;
  393. unsigned long flags;
  394. int ret = 0;
  395. ep = container_of(_ep, struct fotg210_ep, ep);
  396. fotg210 = ep->fotg210;
  397. spin_lock_irqsave(&ep->fotg210->lock, flags);
  398. if (value) {
  399. fotg210_set_epnstall(ep);
  400. ep->stall = 1;
  401. if (wedge)
  402. ep->wedged = 1;
  403. } else {
  404. fotg210_reset_tseq(fotg210, ep->epnum);
  405. fotg210_clear_epnstall(ep);
  406. ep->stall = 0;
  407. ep->wedged = 0;
  408. if (!list_empty(&ep->queue))
  409. fotg210_enable_fifo_int(ep);
  410. }
  411. spin_unlock_irqrestore(&ep->fotg210->lock, flags);
  412. return ret;
  413. }
  414. static int fotg210_ep_set_halt(struct usb_ep *_ep, int value)
  415. {
  416. return fotg210_set_halt_and_wedge(_ep, value, 0);
  417. }
  418. static int fotg210_ep_set_wedge(struct usb_ep *_ep)
  419. {
  420. return fotg210_set_halt_and_wedge(_ep, 1, 1);
  421. }
  422. static void fotg210_ep_fifo_flush(struct usb_ep *_ep)
  423. {
  424. }
  425. static struct usb_ep_ops fotg210_ep_ops = {
  426. .enable = fotg210_ep_enable,
  427. .disable = fotg210_ep_disable,
  428. .alloc_request = fotg210_ep_alloc_request,
  429. .free_request = fotg210_ep_free_request,
  430. .queue = fotg210_ep_queue,
  431. .dequeue = fotg210_ep_dequeue,
  432. .set_halt = fotg210_ep_set_halt,
  433. .fifo_flush = fotg210_ep_fifo_flush,
  434. .set_wedge = fotg210_ep_set_wedge,
  435. };
  436. static void fotg210_clear_tx0byte(struct fotg210_udc *fotg210)
  437. {
  438. u32 value = ioread32(fotg210->reg + FOTG210_TX0BYTE);
  439. value &= ~(TX0BYTE_EP1 | TX0BYTE_EP2 | TX0BYTE_EP3
  440. | TX0BYTE_EP4);
  441. iowrite32(value, fotg210->reg + FOTG210_TX0BYTE);
  442. }
  443. static void fotg210_clear_rx0byte(struct fotg210_udc *fotg210)
  444. {
  445. u32 value = ioread32(fotg210->reg + FOTG210_RX0BYTE);
  446. value &= ~(RX0BYTE_EP1 | RX0BYTE_EP2 | RX0BYTE_EP3
  447. | RX0BYTE_EP4);
  448. iowrite32(value, fotg210->reg + FOTG210_RX0BYTE);
  449. }
  450. /* read 8-byte setup packet only */
  451. static void fotg210_rdsetupp(struct fotg210_udc *fotg210,
  452. u8 *buffer)
  453. {
  454. int i = 0;
  455. u8 *tmp = buffer;
  456. u32 data;
  457. u32 length = 8;
  458. iowrite32(DMATFNR_ACC_CXF, fotg210->reg + FOTG210_DMATFNR);
  459. for (i = (length >> 2); i > 0; i--) {
  460. data = ioread32(fotg210->reg + FOTG210_CXPORT);
  461. *tmp = data & 0xFF;
  462. *(tmp + 1) = (data >> 8) & 0xFF;
  463. *(tmp + 2) = (data >> 16) & 0xFF;
  464. *(tmp + 3) = (data >> 24) & 0xFF;
  465. tmp = tmp + 4;
  466. }
  467. switch (length % 4) {
  468. case 1:
  469. data = ioread32(fotg210->reg + FOTG210_CXPORT);
  470. *tmp = data & 0xFF;
  471. break;
  472. case 2:
  473. data = ioread32(fotg210->reg + FOTG210_CXPORT);
  474. *tmp = data & 0xFF;
  475. *(tmp + 1) = (data >> 8) & 0xFF;
  476. break;
  477. case 3:
  478. data = ioread32(fotg210->reg + FOTG210_CXPORT);
  479. *tmp = data & 0xFF;
  480. *(tmp + 1) = (data >> 8) & 0xFF;
  481. *(tmp + 2) = (data >> 16) & 0xFF;
  482. break;
  483. default:
  484. break;
  485. }
  486. iowrite32(DMATFNR_DISDMA, fotg210->reg + FOTG210_DMATFNR);
  487. }
  488. static void fotg210_set_configuration(struct fotg210_udc *fotg210)
  489. {
  490. u32 value = ioread32(fotg210->reg + FOTG210_DAR);
  491. value |= DAR_AFT_CONF;
  492. iowrite32(value, fotg210->reg + FOTG210_DAR);
  493. }
  494. static void fotg210_set_dev_addr(struct fotg210_udc *fotg210, u32 addr)
  495. {
  496. u32 value = ioread32(fotg210->reg + FOTG210_DAR);
  497. value |= (addr & 0x7F);
  498. iowrite32(value, fotg210->reg + FOTG210_DAR);
  499. }
  500. static void fotg210_set_cxstall(struct fotg210_udc *fotg210)
  501. {
  502. u32 value = ioread32(fotg210->reg + FOTG210_DCFESR);
  503. value |= DCFESR_CX_STL;
  504. iowrite32(value, fotg210->reg + FOTG210_DCFESR);
  505. }
  506. static void fotg210_request_error(struct fotg210_udc *fotg210)
  507. {
  508. fotg210_set_cxstall(fotg210);
  509. pr_err("request error!!\n");
  510. }
  511. static void fotg210_set_address(struct fotg210_udc *fotg210,
  512. struct usb_ctrlrequest *ctrl)
  513. {
  514. if (ctrl->wValue >= 0x0100) {
  515. fotg210_request_error(fotg210);
  516. } else {
  517. fotg210_set_dev_addr(fotg210, ctrl->wValue);
  518. fotg210_set_cxdone(fotg210);
  519. }
  520. }
  521. static void fotg210_set_feature(struct fotg210_udc *fotg210,
  522. struct usb_ctrlrequest *ctrl)
  523. {
  524. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  525. case USB_RECIP_DEVICE:
  526. fotg210_set_cxdone(fotg210);
  527. break;
  528. case USB_RECIP_INTERFACE:
  529. fotg210_set_cxdone(fotg210);
  530. break;
  531. case USB_RECIP_ENDPOINT: {
  532. u8 epnum;
  533. epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  534. if (epnum)
  535. fotg210_set_epnstall(fotg210->ep[epnum]);
  536. else
  537. fotg210_set_cxstall(fotg210);
  538. fotg210_set_cxdone(fotg210);
  539. }
  540. break;
  541. default:
  542. fotg210_request_error(fotg210);
  543. break;
  544. }
  545. }
  546. static void fotg210_clear_feature(struct fotg210_udc *fotg210,
  547. struct usb_ctrlrequest *ctrl)
  548. {
  549. struct fotg210_ep *ep =
  550. fotg210->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK];
  551. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  552. case USB_RECIP_DEVICE:
  553. fotg210_set_cxdone(fotg210);
  554. break;
  555. case USB_RECIP_INTERFACE:
  556. fotg210_set_cxdone(fotg210);
  557. break;
  558. case USB_RECIP_ENDPOINT:
  559. if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) {
  560. if (ep->wedged) {
  561. fotg210_set_cxdone(fotg210);
  562. break;
  563. }
  564. if (ep->stall)
  565. fotg210_set_halt_and_wedge(&ep->ep, 0, 0);
  566. }
  567. fotg210_set_cxdone(fotg210);
  568. break;
  569. default:
  570. fotg210_request_error(fotg210);
  571. break;
  572. }
  573. }
  574. static int fotg210_is_epnstall(struct fotg210_ep *ep)
  575. {
  576. struct fotg210_udc *fotg210 = ep->fotg210;
  577. u32 value;
  578. void __iomem *reg;
  579. reg = (ep->dir_in) ?
  580. fotg210->reg + FOTG210_INEPMPSR(ep->epnum) :
  581. fotg210->reg + FOTG210_OUTEPMPSR(ep->epnum);
  582. value = ioread32(reg);
  583. return value & INOUTEPMPSR_STL_EP ? 1 : 0;
  584. }
  585. static void fotg210_get_status(struct fotg210_udc *fotg210,
  586. struct usb_ctrlrequest *ctrl)
  587. {
  588. u8 epnum;
  589. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  590. case USB_RECIP_DEVICE:
  591. fotg210->ep0_data = 1 << USB_DEVICE_SELF_POWERED;
  592. break;
  593. case USB_RECIP_INTERFACE:
  594. fotg210->ep0_data = 0;
  595. break;
  596. case USB_RECIP_ENDPOINT:
  597. epnum = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
  598. if (epnum)
  599. fotg210->ep0_data =
  600. fotg210_is_epnstall(fotg210->ep[epnum])
  601. << USB_ENDPOINT_HALT;
  602. else
  603. fotg210_request_error(fotg210);
  604. break;
  605. default:
  606. fotg210_request_error(fotg210);
  607. return; /* exit */
  608. }
  609. fotg210->ep0_req->buf = &fotg210->ep0_data;
  610. fotg210->ep0_req->length = 2;
  611. spin_unlock(&fotg210->lock);
  612. fotg210_ep_queue(fotg210->gadget.ep0, fotg210->ep0_req, GFP_KERNEL);
  613. spin_lock(&fotg210->lock);
  614. }
  615. static int fotg210_setup_packet(struct fotg210_udc *fotg210,
  616. struct usb_ctrlrequest *ctrl)
  617. {
  618. u8 *p = (u8 *)ctrl;
  619. u8 ret = 0;
  620. fotg210_rdsetupp(fotg210, p);
  621. fotg210->ep[0]->dir_in = ctrl->bRequestType & USB_DIR_IN;
  622. if (fotg210->gadget.speed == USB_SPEED_UNKNOWN) {
  623. u32 value = ioread32(fotg210->reg + FOTG210_DMCR);
  624. fotg210->gadget.speed = value & DMCR_HS_EN ?
  625. USB_SPEED_HIGH : USB_SPEED_FULL;
  626. }
  627. /* check request */
  628. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  629. switch (ctrl->bRequest) {
  630. case USB_REQ_GET_STATUS:
  631. fotg210_get_status(fotg210, ctrl);
  632. break;
  633. case USB_REQ_CLEAR_FEATURE:
  634. fotg210_clear_feature(fotg210, ctrl);
  635. break;
  636. case USB_REQ_SET_FEATURE:
  637. fotg210_set_feature(fotg210, ctrl);
  638. break;
  639. case USB_REQ_SET_ADDRESS:
  640. fotg210_set_address(fotg210, ctrl);
  641. break;
  642. case USB_REQ_SET_CONFIGURATION:
  643. fotg210_set_configuration(fotg210);
  644. ret = 1;
  645. break;
  646. default:
  647. ret = 1;
  648. break;
  649. }
  650. } else {
  651. ret = 1;
  652. }
  653. return ret;
  654. }
  655. static void fotg210_ep0out(struct fotg210_udc *fotg210)
  656. {
  657. struct fotg210_ep *ep = fotg210->ep[0];
  658. if (!list_empty(&ep->queue) && !ep->dir_in) {
  659. struct fotg210_request *req;
  660. req = list_first_entry(&ep->queue,
  661. struct fotg210_request, queue);
  662. if (req->req.length)
  663. fotg210_start_dma(ep, req);
  664. if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
  665. fotg210_done(ep, req, 0);
  666. } else {
  667. pr_err("%s : empty queue\n", __func__);
  668. }
  669. }
  670. static void fotg210_ep0in(struct fotg210_udc *fotg210)
  671. {
  672. struct fotg210_ep *ep = fotg210->ep[0];
  673. if ((!list_empty(&ep->queue)) && (ep->dir_in)) {
  674. struct fotg210_request *req;
  675. req = list_entry(ep->queue.next,
  676. struct fotg210_request, queue);
  677. if (req->req.length)
  678. fotg210_start_dma(ep, req);
  679. if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
  680. fotg210_done(ep, req, 0);
  681. } else {
  682. fotg210_set_cxdone(fotg210);
  683. }
  684. }
  685. static void fotg210_clear_comabt_int(struct fotg210_udc *fotg210)
  686. {
  687. u32 value = ioread32(fotg210->reg + FOTG210_DISGR0);
  688. value &= ~DISGR0_CX_COMABT_INT;
  689. iowrite32(value, fotg210->reg + FOTG210_DISGR0);
  690. }
  691. static void fotg210_in_fifo_handler(struct fotg210_ep *ep)
  692. {
  693. struct fotg210_request *req = list_entry(ep->queue.next,
  694. struct fotg210_request, queue);
  695. if (req->req.length)
  696. fotg210_start_dma(ep, req);
  697. fotg210_done(ep, req, 0);
  698. }
  699. static void fotg210_out_fifo_handler(struct fotg210_ep *ep)
  700. {
  701. struct fotg210_request *req = list_entry(ep->queue.next,
  702. struct fotg210_request, queue);
  703. fotg210_start_dma(ep, req);
  704. /* finish out transfer */
  705. if (req->req.length == req->req.actual ||
  706. req->req.actual < ep->ep.maxpacket)
  707. fotg210_done(ep, req, 0);
  708. }
  709. static irqreturn_t fotg210_irq(int irq, void *_fotg210)
  710. {
  711. struct fotg210_udc *fotg210 = _fotg210;
  712. u32 int_grp = ioread32(fotg210->reg + FOTG210_DIGR);
  713. u32 int_msk = ioread32(fotg210->reg + FOTG210_DMIGR);
  714. int_grp &= ~int_msk;
  715. spin_lock(&fotg210->lock);
  716. if (int_grp & DIGR_INT_G2) {
  717. void __iomem *reg = fotg210->reg + FOTG210_DISGR2;
  718. u32 int_grp2 = ioread32(reg);
  719. u32 int_msk2 = ioread32(fotg210->reg + FOTG210_DMISGR2);
  720. u32 value;
  721. int_grp2 &= ~int_msk2;
  722. if (int_grp2 & DISGR2_USBRST_INT) {
  723. value = ioread32(reg);
  724. value &= ~DISGR2_USBRST_INT;
  725. iowrite32(value, reg);
  726. pr_info("fotg210 udc reset\n");
  727. }
  728. if (int_grp2 & DISGR2_SUSP_INT) {
  729. value = ioread32(reg);
  730. value &= ~DISGR2_SUSP_INT;
  731. iowrite32(value, reg);
  732. pr_info("fotg210 udc suspend\n");
  733. }
  734. if (int_grp2 & DISGR2_RESM_INT) {
  735. value = ioread32(reg);
  736. value &= ~DISGR2_RESM_INT;
  737. iowrite32(value, reg);
  738. pr_info("fotg210 udc resume\n");
  739. }
  740. if (int_grp2 & DISGR2_ISO_SEQ_ERR_INT) {
  741. value = ioread32(reg);
  742. value &= ~DISGR2_ISO_SEQ_ERR_INT;
  743. iowrite32(value, reg);
  744. pr_info("fotg210 iso sequence error\n");
  745. }
  746. if (int_grp2 & DISGR2_ISO_SEQ_ABORT_INT) {
  747. value = ioread32(reg);
  748. value &= ~DISGR2_ISO_SEQ_ABORT_INT;
  749. iowrite32(value, reg);
  750. pr_info("fotg210 iso sequence abort\n");
  751. }
  752. if (int_grp2 & DISGR2_TX0BYTE_INT) {
  753. fotg210_clear_tx0byte(fotg210);
  754. value = ioread32(reg);
  755. value &= ~DISGR2_TX0BYTE_INT;
  756. iowrite32(value, reg);
  757. pr_info("fotg210 transferred 0 byte\n");
  758. }
  759. if (int_grp2 & DISGR2_RX0BYTE_INT) {
  760. fotg210_clear_rx0byte(fotg210);
  761. value = ioread32(reg);
  762. value &= ~DISGR2_RX0BYTE_INT;
  763. iowrite32(value, reg);
  764. pr_info("fotg210 received 0 byte\n");
  765. }
  766. if (int_grp2 & DISGR2_DMA_ERROR) {
  767. value = ioread32(reg);
  768. value &= ~DISGR2_DMA_ERROR;
  769. iowrite32(value, reg);
  770. }
  771. }
  772. if (int_grp & DIGR_INT_G0) {
  773. void __iomem *reg = fotg210->reg + FOTG210_DISGR0;
  774. u32 int_grp0 = ioread32(reg);
  775. u32 int_msk0 = ioread32(fotg210->reg + FOTG210_DMISGR0);
  776. struct usb_ctrlrequest ctrl;
  777. int_grp0 &= ~int_msk0;
  778. /* the highest priority in this source register */
  779. if (int_grp0 & DISGR0_CX_COMABT_INT) {
  780. fotg210_clear_comabt_int(fotg210);
  781. pr_info("fotg210 CX command abort\n");
  782. }
  783. if (int_grp0 & DISGR0_CX_SETUP_INT) {
  784. if (fotg210_setup_packet(fotg210, &ctrl)) {
  785. spin_unlock(&fotg210->lock);
  786. if (fotg210->driver->setup(&fotg210->gadget,
  787. &ctrl) < 0)
  788. fotg210_set_cxstall(fotg210);
  789. spin_lock(&fotg210->lock);
  790. }
  791. }
  792. if (int_grp0 & DISGR0_CX_COMEND_INT)
  793. pr_info("fotg210 cmd end\n");
  794. if (int_grp0 & DISGR0_CX_IN_INT)
  795. fotg210_ep0in(fotg210);
  796. if (int_grp0 & DISGR0_CX_OUT_INT)
  797. fotg210_ep0out(fotg210);
  798. if (int_grp0 & DISGR0_CX_COMFAIL_INT) {
  799. fotg210_set_cxstall(fotg210);
  800. pr_info("fotg210 ep0 fail\n");
  801. }
  802. }
  803. if (int_grp & DIGR_INT_G1) {
  804. void __iomem *reg = fotg210->reg + FOTG210_DISGR1;
  805. u32 int_grp1 = ioread32(reg);
  806. u32 int_msk1 = ioread32(fotg210->reg + FOTG210_DMISGR1);
  807. int fifo;
  808. int_grp1 &= ~int_msk1;
  809. for (fifo = 0; fifo < FOTG210_MAX_FIFO_NUM; fifo++) {
  810. if (int_grp1 & DISGR1_IN_INT(fifo))
  811. fotg210_in_fifo_handler(fotg210->ep[fifo + 1]);
  812. if ((int_grp1 & DISGR1_OUT_INT(fifo)) ||
  813. (int_grp1 & DISGR1_SPK_INT(fifo)))
  814. fotg210_out_fifo_handler(fotg210->ep[fifo + 1]);
  815. }
  816. }
  817. spin_unlock(&fotg210->lock);
  818. return IRQ_HANDLED;
  819. }
  820. static void fotg210_disable_unplug(struct fotg210_udc *fotg210)
  821. {
  822. u32 reg = ioread32(fotg210->reg + FOTG210_PHYTMSR);
  823. reg &= ~PHYTMSR_UNPLUG;
  824. iowrite32(reg, fotg210->reg + FOTG210_PHYTMSR);
  825. }
  826. static int fotg210_udc_start(struct usb_gadget *g,
  827. struct usb_gadget_driver *driver)
  828. {
  829. struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
  830. u32 value;
  831. /* hook up the driver */
  832. driver->driver.bus = NULL;
  833. fotg210->driver = driver;
  834. /* enable device global interrupt */
  835. value = ioread32(fotg210->reg + FOTG210_DMCR);
  836. value |= DMCR_GLINT_EN;
  837. iowrite32(value, fotg210->reg + FOTG210_DMCR);
  838. return 0;
  839. }
  840. static void fotg210_init(struct fotg210_udc *fotg210)
  841. {
  842. u32 value;
  843. /* disable global interrupt and set int polarity to active high */
  844. iowrite32(GMIR_MHC_INT | GMIR_MOTG_INT | GMIR_INT_POLARITY,
  845. fotg210->reg + FOTG210_GMIR);
  846. /* disable device global interrupt */
  847. value = ioread32(fotg210->reg + FOTG210_DMCR);
  848. value &= ~DMCR_GLINT_EN;
  849. iowrite32(value, fotg210->reg + FOTG210_DMCR);
  850. /* disable all fifo interrupt */
  851. iowrite32(~(u32)0, fotg210->reg + FOTG210_DMISGR1);
  852. /* disable cmd end */
  853. value = ioread32(fotg210->reg + FOTG210_DMISGR0);
  854. value |= DMISGR0_MCX_COMEND;
  855. iowrite32(value, fotg210->reg + FOTG210_DMISGR0);
  856. }
  857. static int fotg210_udc_stop(struct usb_gadget *g)
  858. {
  859. struct fotg210_udc *fotg210 = gadget_to_fotg210(g);
  860. unsigned long flags;
  861. spin_lock_irqsave(&fotg210->lock, flags);
  862. fotg210_init(fotg210);
  863. fotg210->driver = NULL;
  864. spin_unlock_irqrestore(&fotg210->lock, flags);
  865. return 0;
  866. }
  867. static struct usb_gadget_ops fotg210_gadget_ops = {
  868. .udc_start = fotg210_udc_start,
  869. .udc_stop = fotg210_udc_stop,
  870. };
  871. static int fotg210_udc_remove(struct platform_device *pdev)
  872. {
  873. struct fotg210_udc *fotg210 = platform_get_drvdata(pdev);
  874. int i;
  875. usb_del_gadget_udc(&fotg210->gadget);
  876. iounmap(fotg210->reg);
  877. free_irq(platform_get_irq(pdev, 0), fotg210);
  878. fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
  879. for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
  880. kfree(fotg210->ep[i]);
  881. kfree(fotg210);
  882. return 0;
  883. }
  884. static int fotg210_udc_probe(struct platform_device *pdev)
  885. {
  886. struct resource *res, *ires;
  887. struct fotg210_udc *fotg210 = NULL;
  888. struct fotg210_ep *_ep[FOTG210_MAX_NUM_EP];
  889. int ret = 0;
  890. int i;
  891. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  892. if (!res) {
  893. pr_err("platform_get_resource error.\n");
  894. return -ENODEV;
  895. }
  896. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  897. if (!ires) {
  898. pr_err("platform_get_resource IORESOURCE_IRQ error.\n");
  899. return -ENODEV;
  900. }
  901. ret = -ENOMEM;
  902. /* initialize udc */
  903. fotg210 = kzalloc(sizeof(struct fotg210_udc), GFP_KERNEL);
  904. if (fotg210 == NULL)
  905. goto err;
  906. for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
  907. _ep[i] = kzalloc(sizeof(struct fotg210_ep), GFP_KERNEL);
  908. if (_ep[i] == NULL)
  909. goto err_alloc;
  910. fotg210->ep[i] = _ep[i];
  911. }
  912. fotg210->reg = ioremap(res->start, resource_size(res));
  913. if (fotg210->reg == NULL) {
  914. pr_err("ioremap error.\n");
  915. goto err_alloc;
  916. }
  917. spin_lock_init(&fotg210->lock);
  918. platform_set_drvdata(pdev, fotg210);
  919. fotg210->gadget.ops = &fotg210_gadget_ops;
  920. fotg210->gadget.max_speed = USB_SPEED_HIGH;
  921. fotg210->gadget.dev.parent = &pdev->dev;
  922. fotg210->gadget.dev.dma_mask = pdev->dev.dma_mask;
  923. fotg210->gadget.name = udc_name;
  924. INIT_LIST_HEAD(&fotg210->gadget.ep_list);
  925. for (i = 0; i < FOTG210_MAX_NUM_EP; i++) {
  926. struct fotg210_ep *ep = fotg210->ep[i];
  927. if (i) {
  928. INIT_LIST_HEAD(&fotg210->ep[i]->ep.ep_list);
  929. list_add_tail(&fotg210->ep[i]->ep.ep_list,
  930. &fotg210->gadget.ep_list);
  931. }
  932. ep->fotg210 = fotg210;
  933. INIT_LIST_HEAD(&ep->queue);
  934. ep->ep.name = fotg210_ep_name[i];
  935. ep->ep.ops = &fotg210_ep_ops;
  936. usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
  937. if (i == 0) {
  938. ep->ep.caps.type_control = true;
  939. } else {
  940. ep->ep.caps.type_iso = true;
  941. ep->ep.caps.type_bulk = true;
  942. ep->ep.caps.type_int = true;
  943. }
  944. ep->ep.caps.dir_in = true;
  945. ep->ep.caps.dir_out = true;
  946. }
  947. usb_ep_set_maxpacket_limit(&fotg210->ep[0]->ep, 0x40);
  948. fotg210->gadget.ep0 = &fotg210->ep[0]->ep;
  949. INIT_LIST_HEAD(&fotg210->gadget.ep0->ep_list);
  950. fotg210->ep0_req = fotg210_ep_alloc_request(&fotg210->ep[0]->ep,
  951. GFP_KERNEL);
  952. if (fotg210->ep0_req == NULL)
  953. goto err_map;
  954. fotg210_init(fotg210);
  955. fotg210_disable_unplug(fotg210);
  956. ret = request_irq(ires->start, fotg210_irq, IRQF_SHARED,
  957. udc_name, fotg210);
  958. if (ret < 0) {
  959. pr_err("request_irq error (%d)\n", ret);
  960. goto err_req;
  961. }
  962. ret = usb_add_gadget_udc(&pdev->dev, &fotg210->gadget);
  963. if (ret)
  964. goto err_add_udc;
  965. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  966. return 0;
  967. err_add_udc:
  968. free_irq(ires->start, fotg210);
  969. err_req:
  970. fotg210_ep_free_request(&fotg210->ep[0]->ep, fotg210->ep0_req);
  971. err_map:
  972. iounmap(fotg210->reg);
  973. err_alloc:
  974. for (i = 0; i < FOTG210_MAX_NUM_EP; i++)
  975. kfree(fotg210->ep[i]);
  976. kfree(fotg210);
  977. err:
  978. return ret;
  979. }
  980. static struct platform_driver fotg210_driver = {
  981. .driver = {
  982. .name = (char *)udc_name,
  983. },
  984. .probe = fotg210_udc_probe,
  985. .remove = fotg210_udc_remove,
  986. };
  987. module_platform_driver(fotg210_driver);
  988. MODULE_AUTHOR("Yuan-Hsin Chen, Feng-Hsin Chiang <john453@faraday-tech.com>");
  989. MODULE_LICENSE("GPL");
  990. MODULE_DESCRIPTION(DRIVER_DESC);