fsl_mxc_udc.c 3.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125
  1. /*
  2. * Copyright (C) 2009
  3. * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
  4. *
  5. * Description:
  6. * Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c
  7. * driver to function correctly on these systems.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/delay.h>
  16. #include <linux/err.h>
  17. #include <linux/fsl_devices.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/io.h>
  20. #include "fsl_usb2_udc.h"
  21. static struct clk *mxc_ahb_clk;
  22. static struct clk *mxc_per_clk;
  23. static struct clk *mxc_ipg_clk;
  24. /* workaround ENGcm09152 for i.MX35 */
  25. #define MX35_USBPHYCTRL_OFFSET 0x600
  26. #define USBPHYCTRL_OTGBASE_OFFSET 0x8
  27. #define USBPHYCTRL_EVDO (1 << 23)
  28. int fsl_udc_clk_init(struct platform_device *pdev)
  29. {
  30. struct fsl_usb2_platform_data *pdata;
  31. unsigned long freq;
  32. int ret;
  33. pdata = dev_get_platdata(&pdev->dev);
  34. mxc_ipg_clk = devm_clk_get(&pdev->dev, "ipg");
  35. if (IS_ERR(mxc_ipg_clk)) {
  36. dev_err(&pdev->dev, "clk_get(\"ipg\") failed\n");
  37. return PTR_ERR(mxc_ipg_clk);
  38. }
  39. mxc_ahb_clk = devm_clk_get(&pdev->dev, "ahb");
  40. if (IS_ERR(mxc_ahb_clk)) {
  41. dev_err(&pdev->dev, "clk_get(\"ahb\") failed\n");
  42. return PTR_ERR(mxc_ahb_clk);
  43. }
  44. mxc_per_clk = devm_clk_get(&pdev->dev, "per");
  45. if (IS_ERR(mxc_per_clk)) {
  46. dev_err(&pdev->dev, "clk_get(\"per\") failed\n");
  47. return PTR_ERR(mxc_per_clk);
  48. }
  49. clk_prepare_enable(mxc_ipg_clk);
  50. clk_prepare_enable(mxc_ahb_clk);
  51. clk_prepare_enable(mxc_per_clk);
  52. /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */
  53. if (!strcmp(pdev->id_entry->name, "imx-udc-mx27")) {
  54. freq = clk_get_rate(mxc_per_clk);
  55. if (pdata->phy_mode != FSL_USB2_PHY_ULPI &&
  56. (freq < 59999000 || freq > 60001000)) {
  57. dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq);
  58. ret = -EINVAL;
  59. goto eclkrate;
  60. }
  61. }
  62. return 0;
  63. eclkrate:
  64. clk_disable_unprepare(mxc_ipg_clk);
  65. clk_disable_unprepare(mxc_ahb_clk);
  66. clk_disable_unprepare(mxc_per_clk);
  67. mxc_per_clk = NULL;
  68. return ret;
  69. }
  70. int fsl_udc_clk_finalize(struct platform_device *pdev)
  71. {
  72. struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
  73. int ret = 0;
  74. /* workaround ENGcm09152 for i.MX35 */
  75. if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) {
  76. unsigned int v;
  77. struct resource *res = platform_get_resource
  78. (pdev, IORESOURCE_MEM, 0);
  79. void __iomem *phy_regs = ioremap(res->start +
  80. MX35_USBPHYCTRL_OFFSET, 512);
  81. if (!phy_regs) {
  82. dev_err(&pdev->dev, "ioremap for phy address fails\n");
  83. ret = -EINVAL;
  84. goto ioremap_err;
  85. }
  86. v = readl(phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
  87. writel(v | USBPHYCTRL_EVDO,
  88. phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
  89. iounmap(phy_regs);
  90. }
  91. ioremap_err:
  92. /* ULPI transceivers don't need usbpll */
  93. if (pdata->phy_mode == FSL_USB2_PHY_ULPI) {
  94. clk_disable_unprepare(mxc_per_clk);
  95. mxc_per_clk = NULL;
  96. }
  97. return ret;
  98. }
  99. void fsl_udc_clk_release(void)
  100. {
  101. if (mxc_per_clk)
  102. clk_disable_unprepare(mxc_per_clk);
  103. clk_disable_unprepare(mxc_ahb_clk);
  104. clk_disable_unprepare(mxc_ipg_clk);
  105. }