fsl_qe_udc.h 12 KB

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  1. /*
  2. * drivers/usb/gadget/qe_udc.h
  3. *
  4. * Copyright (C) 2006-2008 Freescale Semiconductor, Inc. All rights reserved.
  5. *
  6. * Xiaobo Xie <X.Xie@freescale.com>
  7. * Li Yang <leoli@freescale.com>
  8. *
  9. * Description:
  10. * Freescale USB device/endpoint management registers
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or (at
  15. * your option) any later version.
  16. */
  17. #ifndef __FSL_QE_UDC_H
  18. #define __FSL_QE_UDC_H
  19. /* SoC type */
  20. #define PORT_CPM 0
  21. #define PORT_QE 1
  22. #define USB_MAX_ENDPOINTS 4
  23. #define USB_MAX_PIPES USB_MAX_ENDPOINTS
  24. #define USB_EP0_MAX_SIZE 64
  25. #define USB_MAX_CTRL_PAYLOAD 0x4000
  26. #define USB_BDRING_LEN 16
  27. #define USB_BDRING_LEN_RX 256
  28. #define USB_BDRING_LEN_TX 16
  29. #define MIN_EMPTY_BDS 128
  30. #define MAX_DATA_BDS 8
  31. #define USB_CRC_SIZE 2
  32. #define USB_DIR_BOTH 0x88
  33. #define R_BUF_MAXSIZE 0x800
  34. #define USB_EP_PARA_ALIGNMENT 32
  35. /* USB Mode Register bit define */
  36. #define USB_MODE_EN 0x01
  37. #define USB_MODE_HOST 0x02
  38. #define USB_MODE_TEST 0x04
  39. #define USB_MODE_SFTE 0x08
  40. #define USB_MODE_RESUME 0x40
  41. #define USB_MODE_LSS 0x80
  42. /* USB Slave Address Register Mask */
  43. #define USB_SLVADDR_MASK 0x7F
  44. /* USB Endpoint register define */
  45. #define USB_EPNUM_MASK 0xF000
  46. #define USB_EPNUM_SHIFT 12
  47. #define USB_TRANS_MODE_SHIFT 8
  48. #define USB_TRANS_CTR 0x0000
  49. #define USB_TRANS_INT 0x0100
  50. #define USB_TRANS_BULK 0x0200
  51. #define USB_TRANS_ISO 0x0300
  52. #define USB_EP_MF 0x0020
  53. #define USB_EP_RTE 0x0010
  54. #define USB_THS_SHIFT 2
  55. #define USB_THS_MASK 0x000c
  56. #define USB_THS_NORMAL 0x0
  57. #define USB_THS_IGNORE_IN 0x0004
  58. #define USB_THS_NACK 0x0008
  59. #define USB_THS_STALL 0x000c
  60. #define USB_RHS_SHIFT 0
  61. #define USB_RHS_MASK 0x0003
  62. #define USB_RHS_NORMAL 0x0
  63. #define USB_RHS_IGNORE_OUT 0x0001
  64. #define USB_RHS_NACK 0x0002
  65. #define USB_RHS_STALL 0x0003
  66. #define USB_RTHS_MASK 0x000f
  67. /* USB Command Register define */
  68. #define USB_CMD_STR_FIFO 0x80
  69. #define USB_CMD_FLUSH_FIFO 0x40
  70. #define USB_CMD_ISFT 0x20
  71. #define USB_CMD_DSFT 0x10
  72. #define USB_CMD_EP_MASK 0x03
  73. /* USB Event and Mask Register define */
  74. #define USB_E_MSF_MASK 0x0800
  75. #define USB_E_SFT_MASK 0x0400
  76. #define USB_E_RESET_MASK 0x0200
  77. #define USB_E_IDLE_MASK 0x0100
  78. #define USB_E_TXE4_MASK 0x0080
  79. #define USB_E_TXE3_MASK 0x0040
  80. #define USB_E_TXE2_MASK 0x0020
  81. #define USB_E_TXE1_MASK 0x0010
  82. #define USB_E_SOF_MASK 0x0008
  83. #define USB_E_BSY_MASK 0x0004
  84. #define USB_E_TXB_MASK 0x0002
  85. #define USB_E_RXB_MASK 0x0001
  86. #define USBER_ALL_CLEAR 0x0fff
  87. #define USB_E_DEFAULT_DEVICE (USB_E_RESET_MASK | USB_E_TXE4_MASK | \
  88. USB_E_TXE3_MASK | USB_E_TXE2_MASK | \
  89. USB_E_TXE1_MASK | USB_E_BSY_MASK | \
  90. USB_E_TXB_MASK | USB_E_RXB_MASK)
  91. #define USB_E_TXE_MASK (USB_E_TXE4_MASK | USB_E_TXE3_MASK|\
  92. USB_E_TXE2_MASK | USB_E_TXE1_MASK)
  93. /* USB Status Register define */
  94. #define USB_IDLE_STATUS_MASK 0x01
  95. /* USB Start of Frame Timer */
  96. #define USB_USSFT_MASK 0x3FFF
  97. /* USB Frame Number Register */
  98. #define USB_USFRN_MASK 0xFFFF
  99. struct usb_device_para{
  100. u16 epptr[4];
  101. u32 rstate;
  102. u32 rptr;
  103. u16 frame_n;
  104. u16 rbcnt;
  105. u32 rtemp;
  106. u32 rxusb_data;
  107. u16 rxuptr;
  108. u8 reso[2];
  109. u32 softbl;
  110. u8 sofucrctemp;
  111. };
  112. struct usb_ep_para{
  113. u16 rbase;
  114. u16 tbase;
  115. u8 rbmr;
  116. u8 tbmr;
  117. u16 mrblr;
  118. u16 rbptr;
  119. u16 tbptr;
  120. u32 tstate;
  121. u32 tptr;
  122. u16 tcrc;
  123. u16 tbcnt;
  124. u32 ttemp;
  125. u16 txusbu_ptr;
  126. u8 reserve[2];
  127. };
  128. #define USB_BUSMODE_GBL 0x20
  129. #define USB_BUSMODE_BO_MASK 0x18
  130. #define USB_BUSMODE_BO_SHIFT 0x3
  131. #define USB_BUSMODE_BE 0x2
  132. #define USB_BUSMODE_CETM 0x04
  133. #define USB_BUSMODE_DTB 0x02
  134. /* Endpoint basic handle */
  135. #define ep_index(EP) ((EP)->ep.desc->bEndpointAddress & 0xF)
  136. #define ep_maxpacket(EP) ((EP)->ep.maxpacket)
  137. #define ep_is_in(EP) ((ep_index(EP) == 0) ? (EP->udc->ep0_dir == \
  138. USB_DIR_IN) : ((EP)->ep.desc->bEndpointAddress \
  139. & USB_DIR_IN) == USB_DIR_IN)
  140. /* ep0 transfer state */
  141. #define WAIT_FOR_SETUP 0
  142. #define DATA_STATE_XMIT 1
  143. #define DATA_STATE_NEED_ZLP 2
  144. #define WAIT_FOR_OUT_STATUS 3
  145. #define DATA_STATE_RECV 4
  146. /* ep tramsfer mode */
  147. #define USBP_TM_CTL 0
  148. #define USBP_TM_ISO 1
  149. #define USBP_TM_BULK 2
  150. #define USBP_TM_INT 3
  151. /*-----------------------------------------------------------------------------
  152. USB RX And TX DATA Frame
  153. -----------------------------------------------------------------------------*/
  154. struct qe_frame{
  155. u8 *data;
  156. u32 len;
  157. u32 status;
  158. u32 info;
  159. void *privdata;
  160. struct list_head node;
  161. };
  162. /* Frame structure, info field. */
  163. #define PID_DATA0 0x80000000 /* Data toggle zero */
  164. #define PID_DATA1 0x40000000 /* Data toggle one */
  165. #define PID_SETUP 0x20000000 /* setup bit */
  166. #define SETUP_STATUS 0x10000000 /* setup status bit */
  167. #define SETADDR_STATUS 0x08000000 /* setupup address status bit */
  168. #define NO_REQ 0x04000000 /* Frame without request */
  169. #define HOST_DATA 0x02000000 /* Host data frame */
  170. #define FIRST_PACKET_IN_FRAME 0x01000000 /* first packet in the frame */
  171. #define TOKEN_FRAME 0x00800000 /* Host token frame */
  172. #define ZLP 0x00400000 /* Zero length packet */
  173. #define IN_TOKEN_FRAME 0x00200000 /* In token package */
  174. #define OUT_TOKEN_FRAME 0x00100000 /* Out token package */
  175. #define SETUP_TOKEN_FRAME 0x00080000 /* Setup token package */
  176. #define STALL_FRAME 0x00040000 /* Stall handshake */
  177. #define NACK_FRAME 0x00020000 /* Nack handshake */
  178. #define NO_PID 0x00010000 /* No send PID */
  179. #define NO_CRC 0x00008000 /* No send CRC */
  180. #define HOST_COMMAND 0x00004000 /* Host command frame */
  181. /* Frame status field */
  182. /* Receive side */
  183. #define FRAME_OK 0x00000000 /* Frame transmitted or received OK */
  184. #define FRAME_ERROR 0x80000000 /* Error occurred on frame */
  185. #define START_FRAME_LOST 0x40000000 /* START_FRAME_LOST */
  186. #define END_FRAME_LOST 0x20000000 /* END_FRAME_LOST */
  187. #define RX_ER_NONOCT 0x10000000 /* Rx Non Octet Aligned Packet */
  188. #define RX_ER_BITSTUFF 0x08000000 /* Frame Aborted --Received packet
  189. with bit stuff error */
  190. #define RX_ER_CRC 0x04000000 /* Received packet with CRC error */
  191. #define RX_ER_OVERUN 0x02000000 /* Over-run occurred on reception */
  192. #define RX_ER_PID 0x01000000 /* Wrong PID received */
  193. /* Tranmit side */
  194. #define TX_ER_NAK 0x00800000 /* Received NAK handshake */
  195. #define TX_ER_STALL 0x00400000 /* Received STALL handshake */
  196. #define TX_ER_TIMEOUT 0x00200000 /* Transmit time out */
  197. #define TX_ER_UNDERUN 0x00100000 /* Transmit underrun */
  198. #define FRAME_INPROGRESS 0x00080000 /* Frame is being transmitted */
  199. #define ER_DATA_UNDERUN 0x00040000 /* Frame is shorter then expected */
  200. #define ER_DATA_OVERUN 0x00020000 /* Frame is longer then expected */
  201. /* QE USB frame operation functions */
  202. #define frame_get_length(frm) (frm->len)
  203. #define frame_set_length(frm, leng) (frm->len = leng)
  204. #define frame_get_data(frm) (frm->data)
  205. #define frame_set_data(frm, dat) (frm->data = dat)
  206. #define frame_get_info(frm) (frm->info)
  207. #define frame_set_info(frm, inf) (frm->info = inf)
  208. #define frame_get_status(frm) (frm->status)
  209. #define frame_set_status(frm, stat) (frm->status = stat)
  210. #define frame_get_privdata(frm) (frm->privdata)
  211. #define frame_set_privdata(frm, dat) (frm->privdata = dat)
  212. static inline void qe_frame_clean(struct qe_frame *frm)
  213. {
  214. frame_set_data(frm, NULL);
  215. frame_set_length(frm, 0);
  216. frame_set_status(frm, FRAME_OK);
  217. frame_set_info(frm, 0);
  218. frame_set_privdata(frm, NULL);
  219. }
  220. static inline void qe_frame_init(struct qe_frame *frm)
  221. {
  222. qe_frame_clean(frm);
  223. INIT_LIST_HEAD(&(frm->node));
  224. }
  225. struct qe_req {
  226. struct usb_request req;
  227. struct list_head queue;
  228. /* ep_queue() func will add
  229. a request->queue into a udc_ep->queue 'd tail */
  230. struct qe_ep *ep;
  231. unsigned mapped:1;
  232. };
  233. struct qe_ep {
  234. struct usb_ep ep;
  235. struct list_head queue;
  236. struct qe_udc *udc;
  237. struct usb_gadget *gadget;
  238. u8 state;
  239. struct qe_bd __iomem *rxbase;
  240. struct qe_bd __iomem *n_rxbd;
  241. struct qe_bd __iomem *e_rxbd;
  242. struct qe_bd __iomem *txbase;
  243. struct qe_bd __iomem *n_txbd;
  244. struct qe_bd __iomem *c_txbd;
  245. struct qe_frame *rxframe;
  246. u8 *rxbuffer;
  247. dma_addr_t rxbuf_d;
  248. u8 rxbufmap;
  249. unsigned char localnack;
  250. int has_data;
  251. struct qe_frame *txframe;
  252. struct qe_req *tx_req;
  253. int sent; /*data already sent */
  254. int last; /*data sent in the last time*/
  255. u8 dir;
  256. u8 epnum;
  257. u8 tm; /* transfer mode */
  258. u8 data01;
  259. u8 init;
  260. u8 already_seen;
  261. u8 enable_tasklet;
  262. u8 setup_stage;
  263. u32 last_io; /* timestamp */
  264. char name[14];
  265. unsigned double_buf:1;
  266. unsigned stopped:1;
  267. unsigned fnf:1;
  268. unsigned has_dma:1;
  269. u8 ackwait;
  270. u8 dma_channel;
  271. u16 dma_counter;
  272. int lch;
  273. struct timer_list timer;
  274. };
  275. struct qe_udc {
  276. struct usb_gadget gadget;
  277. struct usb_gadget_driver *driver;
  278. struct device *dev;
  279. struct qe_ep eps[USB_MAX_ENDPOINTS];
  280. struct usb_ctrlrequest local_setup_buff;
  281. spinlock_t lock; /* lock for set/config qe_udc */
  282. unsigned long soc_type; /* QE or CPM soc */
  283. struct qe_req *status_req; /* ep0 status request */
  284. /* USB and EP Parameter Block pointer */
  285. struct usb_device_para __iomem *usb_param;
  286. struct usb_ep_para __iomem *ep_param[4];
  287. u32 max_pipes; /* Device max pipes */
  288. u32 max_use_endpts; /* Max endpointes to be used */
  289. u32 bus_reset; /* Device is bus reseting */
  290. u32 resume_state; /* USB state to resume*/
  291. u32 usb_state; /* USB current state */
  292. u32 usb_next_state; /* USB next state */
  293. u32 ep0_state; /* Enpoint zero state */
  294. u32 ep0_dir; /* Enpoint zero direction: can be
  295. USB_DIR_IN or USB_DIR_OUT*/
  296. u32 usb_sof_count; /* SOF count */
  297. u32 errors; /* USB ERRORs count */
  298. u8 *tmpbuf;
  299. u32 c_start;
  300. u32 c_end;
  301. u8 *nullbuf;
  302. u8 *statusbuf;
  303. dma_addr_t nullp;
  304. u8 nullmap;
  305. u8 device_address; /* Device USB address */
  306. unsigned int usb_clock;
  307. unsigned int usb_irq;
  308. struct usb_ctlr __iomem *usb_regs;
  309. struct tasklet_struct rx_tasklet;
  310. struct completion *done; /* to make sure release() is done */
  311. };
  312. #define EP_STATE_IDLE 0
  313. #define EP_STATE_NACK 1
  314. #define EP_STATE_STALL 2
  315. /*
  316. * transmit BD's status
  317. */
  318. #define T_R 0x80000000 /* ready bit */
  319. #define T_W 0x20000000 /* wrap bit */
  320. #define T_I 0x10000000 /* interrupt on completion */
  321. #define T_L 0x08000000 /* last */
  322. #define T_TC 0x04000000 /* transmit CRC */
  323. #define T_CNF 0x02000000 /* wait for transmit confirm */
  324. #define T_LSP 0x01000000 /* Low-speed transaction */
  325. #define T_PID 0x00c00000 /* packet id */
  326. #define T_NAK 0x00100000 /* No ack. */
  327. #define T_STAL 0x00080000 /* Stall received */
  328. #define T_TO 0x00040000 /* time out */
  329. #define T_UN 0x00020000 /* underrun */
  330. #define DEVICE_T_ERROR (T_UN | T_TO)
  331. #define HOST_T_ERROR (T_UN | T_TO | T_NAK | T_STAL)
  332. #define DEVICE_T_BD_MASK DEVICE_T_ERROR
  333. #define HOST_T_BD_MASK HOST_T_ERROR
  334. #define T_PID_SHIFT 6
  335. #define T_PID_DATA0 0x00800000 /* Data 0 toggle */
  336. #define T_PID_DATA1 0x00c00000 /* Data 1 toggle */
  337. /*
  338. * receive BD's status
  339. */
  340. #define R_E 0x80000000 /* buffer empty */
  341. #define R_W 0x20000000 /* wrap bit */
  342. #define R_I 0x10000000 /* interrupt on reception */
  343. #define R_L 0x08000000 /* last */
  344. #define R_F 0x04000000 /* first */
  345. #define R_PID 0x00c00000 /* packet id */
  346. #define R_NO 0x00100000 /* Rx Non Octet Aligned Packet */
  347. #define R_AB 0x00080000 /* Frame Aborted */
  348. #define R_CR 0x00040000 /* CRC Error */
  349. #define R_OV 0x00020000 /* Overrun */
  350. #define R_ERROR (R_NO | R_AB | R_CR | R_OV)
  351. #define R_BD_MASK R_ERROR
  352. #define R_PID_DATA0 0x00000000
  353. #define R_PID_DATA1 0x00400000
  354. #define R_PID_SETUP 0x00800000
  355. #define CPM_USB_STOP_TX 0x2e600000
  356. #define CPM_USB_RESTART_TX 0x2e600000
  357. #define CPM_USB_STOP_TX_OPCODE 0x0a
  358. #define CPM_USB_RESTART_TX_OPCODE 0x0b
  359. #define CPM_USB_EP_SHIFT 5
  360. #endif /* __FSL_QE_UDC_H */