fusb300_udc.c 36 KB

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  1. /*
  2. * Fusb300 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2010 Faraday Technology Corp.
  5. *
  6. * Author : Yuan-hsin Chen <yhchen@faraday-tech.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. */
  12. #include <linux/dma-mapping.h>
  13. #include <linux/err.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/module.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/usb/ch9.h>
  19. #include <linux/usb/gadget.h>
  20. #include "fusb300_udc.h"
  21. MODULE_DESCRIPTION("FUSB300 USB gadget driver");
  22. MODULE_LICENSE("GPL");
  23. MODULE_AUTHOR("Yuan-Hsin Chen, Feng-Hsin Chiang <john453@faraday-tech.com>");
  24. MODULE_ALIAS("platform:fusb300_udc");
  25. #define DRIVER_VERSION "20 October 2010"
  26. static const char udc_name[] = "fusb300_udc";
  27. static const char * const fusb300_ep_name[] = {
  28. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7", "ep8", "ep9",
  29. "ep10", "ep11", "ep12", "ep13", "ep14", "ep15"
  30. };
  31. static void done(struct fusb300_ep *ep, struct fusb300_request *req,
  32. int status);
  33. static void fusb300_enable_bit(struct fusb300 *fusb300, u32 offset,
  34. u32 value)
  35. {
  36. u32 reg = ioread32(fusb300->reg + offset);
  37. reg |= value;
  38. iowrite32(reg, fusb300->reg + offset);
  39. }
  40. static void fusb300_disable_bit(struct fusb300 *fusb300, u32 offset,
  41. u32 value)
  42. {
  43. u32 reg = ioread32(fusb300->reg + offset);
  44. reg &= ~value;
  45. iowrite32(reg, fusb300->reg + offset);
  46. }
  47. static void fusb300_ep_setting(struct fusb300_ep *ep,
  48. struct fusb300_ep_info info)
  49. {
  50. ep->epnum = info.epnum;
  51. ep->type = info.type;
  52. }
  53. static int fusb300_ep_release(struct fusb300_ep *ep)
  54. {
  55. if (!ep->epnum)
  56. return 0;
  57. ep->epnum = 0;
  58. ep->stall = 0;
  59. ep->wedged = 0;
  60. return 0;
  61. }
  62. static void fusb300_set_fifo_entry(struct fusb300 *fusb300,
  63. u32 ep)
  64. {
  65. u32 val = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  66. val &= ~FUSB300_EPSET1_FIFOENTRY_MSK;
  67. val |= FUSB300_EPSET1_FIFOENTRY(FUSB300_FIFO_ENTRY_NUM);
  68. iowrite32(val, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  69. }
  70. static void fusb300_set_start_entry(struct fusb300 *fusb300,
  71. u8 ep)
  72. {
  73. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  74. u32 start_entry = fusb300->fifo_entry_num * FUSB300_FIFO_ENTRY_NUM;
  75. reg &= ~FUSB300_EPSET1_START_ENTRY_MSK ;
  76. reg |= FUSB300_EPSET1_START_ENTRY(start_entry);
  77. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  78. if (fusb300->fifo_entry_num == FUSB300_MAX_FIFO_ENTRY) {
  79. fusb300->fifo_entry_num = 0;
  80. fusb300->addrofs = 0;
  81. pr_err("fifo entry is over the maximum number!\n");
  82. } else
  83. fusb300->fifo_entry_num++;
  84. }
  85. /* set fusb300_set_start_entry first before fusb300_set_epaddrofs */
  86. static void fusb300_set_epaddrofs(struct fusb300 *fusb300,
  87. struct fusb300_ep_info info)
  88. {
  89. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  90. reg &= ~FUSB300_EPSET2_ADDROFS_MSK;
  91. reg |= FUSB300_EPSET2_ADDROFS(fusb300->addrofs);
  92. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  93. fusb300->addrofs += (info.maxpacket + 7) / 8 * FUSB300_FIFO_ENTRY_NUM;
  94. }
  95. static void ep_fifo_setting(struct fusb300 *fusb300,
  96. struct fusb300_ep_info info)
  97. {
  98. fusb300_set_fifo_entry(fusb300, info.epnum);
  99. fusb300_set_start_entry(fusb300, info.epnum);
  100. fusb300_set_epaddrofs(fusb300, info);
  101. }
  102. static void fusb300_set_eptype(struct fusb300 *fusb300,
  103. struct fusb300_ep_info info)
  104. {
  105. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  106. reg &= ~FUSB300_EPSET1_TYPE_MSK;
  107. reg |= FUSB300_EPSET1_TYPE(info.type);
  108. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  109. }
  110. static void fusb300_set_epdir(struct fusb300 *fusb300,
  111. struct fusb300_ep_info info)
  112. {
  113. u32 reg;
  114. if (!info.dir_in)
  115. return;
  116. reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  117. reg &= ~FUSB300_EPSET1_DIR_MSK;
  118. reg |= FUSB300_EPSET1_DIRIN;
  119. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  120. }
  121. static void fusb300_set_ep_active(struct fusb300 *fusb300,
  122. u8 ep)
  123. {
  124. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  125. reg |= FUSB300_EPSET1_ACTEN;
  126. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(ep));
  127. }
  128. static void fusb300_set_epmps(struct fusb300 *fusb300,
  129. struct fusb300_ep_info info)
  130. {
  131. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  132. reg &= ~FUSB300_EPSET2_MPS_MSK;
  133. reg |= FUSB300_EPSET2_MPS(info.maxpacket);
  134. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET2(info.epnum));
  135. }
  136. static void fusb300_set_interval(struct fusb300 *fusb300,
  137. struct fusb300_ep_info info)
  138. {
  139. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  140. reg &= ~FUSB300_EPSET1_INTERVAL(0x7);
  141. reg |= FUSB300_EPSET1_INTERVAL(info.interval);
  142. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  143. }
  144. static void fusb300_set_bwnum(struct fusb300 *fusb300,
  145. struct fusb300_ep_info info)
  146. {
  147. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  148. reg &= ~FUSB300_EPSET1_BWNUM(0x3);
  149. reg |= FUSB300_EPSET1_BWNUM(info.bw_num);
  150. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET1(info.epnum));
  151. }
  152. static void set_ep_reg(struct fusb300 *fusb300,
  153. struct fusb300_ep_info info)
  154. {
  155. fusb300_set_eptype(fusb300, info);
  156. fusb300_set_epdir(fusb300, info);
  157. fusb300_set_epmps(fusb300, info);
  158. if (info.interval)
  159. fusb300_set_interval(fusb300, info);
  160. if (info.bw_num)
  161. fusb300_set_bwnum(fusb300, info);
  162. fusb300_set_ep_active(fusb300, info.epnum);
  163. }
  164. static int config_ep(struct fusb300_ep *ep,
  165. const struct usb_endpoint_descriptor *desc)
  166. {
  167. struct fusb300 *fusb300 = ep->fusb300;
  168. struct fusb300_ep_info info;
  169. ep->ep.desc = desc;
  170. info.interval = 0;
  171. info.addrofs = 0;
  172. info.bw_num = 0;
  173. info.type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  174. info.dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
  175. info.maxpacket = usb_endpoint_maxp(desc);
  176. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  177. if ((info.type == USB_ENDPOINT_XFER_INT) ||
  178. (info.type == USB_ENDPOINT_XFER_ISOC)) {
  179. info.interval = desc->bInterval;
  180. if (info.type == USB_ENDPOINT_XFER_ISOC)
  181. info.bw_num = ((desc->wMaxPacketSize & 0x1800) >> 11);
  182. }
  183. ep_fifo_setting(fusb300, info);
  184. set_ep_reg(fusb300, info);
  185. fusb300_ep_setting(ep, info);
  186. fusb300->ep[info.epnum] = ep;
  187. return 0;
  188. }
  189. static int fusb300_enable(struct usb_ep *_ep,
  190. const struct usb_endpoint_descriptor *desc)
  191. {
  192. struct fusb300_ep *ep;
  193. ep = container_of(_ep, struct fusb300_ep, ep);
  194. if (ep->fusb300->reenum) {
  195. ep->fusb300->fifo_entry_num = 0;
  196. ep->fusb300->addrofs = 0;
  197. ep->fusb300->reenum = 0;
  198. }
  199. return config_ep(ep, desc);
  200. }
  201. static int fusb300_disable(struct usb_ep *_ep)
  202. {
  203. struct fusb300_ep *ep;
  204. struct fusb300_request *req;
  205. unsigned long flags;
  206. ep = container_of(_ep, struct fusb300_ep, ep);
  207. BUG_ON(!ep);
  208. while (!list_empty(&ep->queue)) {
  209. req = list_entry(ep->queue.next, struct fusb300_request, queue);
  210. spin_lock_irqsave(&ep->fusb300->lock, flags);
  211. done(ep, req, -ECONNRESET);
  212. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  213. }
  214. return fusb300_ep_release(ep);
  215. }
  216. static struct usb_request *fusb300_alloc_request(struct usb_ep *_ep,
  217. gfp_t gfp_flags)
  218. {
  219. struct fusb300_request *req;
  220. req = kzalloc(sizeof(struct fusb300_request), gfp_flags);
  221. if (!req)
  222. return NULL;
  223. INIT_LIST_HEAD(&req->queue);
  224. return &req->req;
  225. }
  226. static void fusb300_free_request(struct usb_ep *_ep, struct usb_request *_req)
  227. {
  228. struct fusb300_request *req;
  229. req = container_of(_req, struct fusb300_request, req);
  230. kfree(req);
  231. }
  232. static int enable_fifo_int(struct fusb300_ep *ep)
  233. {
  234. struct fusb300 *fusb300 = ep->fusb300;
  235. if (ep->epnum) {
  236. fusb300_enable_bit(fusb300, FUSB300_OFFSET_IGER0,
  237. FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum));
  238. } else {
  239. pr_err("can't enable_fifo_int ep0\n");
  240. return -EINVAL;
  241. }
  242. return 0;
  243. }
  244. static int disable_fifo_int(struct fusb300_ep *ep)
  245. {
  246. struct fusb300 *fusb300 = ep->fusb300;
  247. if (ep->epnum) {
  248. fusb300_disable_bit(fusb300, FUSB300_OFFSET_IGER0,
  249. FUSB300_IGER0_EEPn_FIFO_INT(ep->epnum));
  250. } else {
  251. pr_err("can't disable_fifo_int ep0\n");
  252. return -EINVAL;
  253. }
  254. return 0;
  255. }
  256. static void fusb300_set_cxlen(struct fusb300 *fusb300, u32 length)
  257. {
  258. u32 reg;
  259. reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR);
  260. reg &= ~FUSB300_CSR_LEN_MSK;
  261. reg |= FUSB300_CSR_LEN(length);
  262. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_CSR);
  263. }
  264. /* write data to cx fifo */
  265. static void fusb300_wrcxf(struct fusb300_ep *ep,
  266. struct fusb300_request *req)
  267. {
  268. int i = 0;
  269. u8 *tmp;
  270. u32 data;
  271. struct fusb300 *fusb300 = ep->fusb300;
  272. u32 length = req->req.length - req->req.actual;
  273. tmp = req->req.buf + req->req.actual;
  274. if (length > SS_CTL_MAX_PACKET_SIZE) {
  275. fusb300_set_cxlen(fusb300, SS_CTL_MAX_PACKET_SIZE);
  276. for (i = (SS_CTL_MAX_PACKET_SIZE >> 2); i > 0; i--) {
  277. data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 |
  278. *(tmp + 3) << 24;
  279. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  280. tmp += 4;
  281. }
  282. req->req.actual += SS_CTL_MAX_PACKET_SIZE;
  283. } else { /* length is less than max packet size */
  284. fusb300_set_cxlen(fusb300, length);
  285. for (i = length >> 2; i > 0; i--) {
  286. data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16 |
  287. *(tmp + 3) << 24;
  288. printk(KERN_DEBUG " 0x%x\n", data);
  289. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  290. tmp = tmp + 4;
  291. }
  292. switch (length % 4) {
  293. case 1:
  294. data = *tmp;
  295. printk(KERN_DEBUG " 0x%x\n", data);
  296. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  297. break;
  298. case 2:
  299. data = *tmp | *(tmp + 1) << 8;
  300. printk(KERN_DEBUG " 0x%x\n", data);
  301. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  302. break;
  303. case 3:
  304. data = *tmp | *(tmp + 1) << 8 | *(tmp + 2) << 16;
  305. printk(KERN_DEBUG " 0x%x\n", data);
  306. iowrite32(data, fusb300->reg + FUSB300_OFFSET_CXPORT);
  307. break;
  308. default:
  309. break;
  310. }
  311. req->req.actual += length;
  312. }
  313. }
  314. static void fusb300_set_epnstall(struct fusb300 *fusb300, u8 ep)
  315. {
  316. fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep),
  317. FUSB300_EPSET0_STL);
  318. }
  319. static void fusb300_clear_epnstall(struct fusb300 *fusb300, u8 ep)
  320. {
  321. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
  322. if (reg & FUSB300_EPSET0_STL) {
  323. printk(KERN_DEBUG "EP%d stall... Clear!!\n", ep);
  324. reg |= FUSB300_EPSET0_STL_CLR;
  325. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
  326. }
  327. }
  328. static void ep0_queue(struct fusb300_ep *ep, struct fusb300_request *req)
  329. {
  330. if (ep->fusb300->ep0_dir) { /* if IN */
  331. if (req->req.length) {
  332. fusb300_wrcxf(ep, req);
  333. } else
  334. printk(KERN_DEBUG "%s : req->req.length = 0x%x\n",
  335. __func__, req->req.length);
  336. if ((req->req.length == req->req.actual) ||
  337. (req->req.actual < ep->ep.maxpacket))
  338. done(ep, req, 0);
  339. } else { /* OUT */
  340. if (!req->req.length)
  341. done(ep, req, 0);
  342. else
  343. fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER1,
  344. FUSB300_IGER1_CX_OUT_INT);
  345. }
  346. }
  347. static int fusb300_queue(struct usb_ep *_ep, struct usb_request *_req,
  348. gfp_t gfp_flags)
  349. {
  350. struct fusb300_ep *ep;
  351. struct fusb300_request *req;
  352. unsigned long flags;
  353. int request = 0;
  354. ep = container_of(_ep, struct fusb300_ep, ep);
  355. req = container_of(_req, struct fusb300_request, req);
  356. if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN)
  357. return -ESHUTDOWN;
  358. spin_lock_irqsave(&ep->fusb300->lock, flags);
  359. if (list_empty(&ep->queue))
  360. request = 1;
  361. list_add_tail(&req->queue, &ep->queue);
  362. req->req.actual = 0;
  363. req->req.status = -EINPROGRESS;
  364. if (ep->ep.desc == NULL) /* ep0 */
  365. ep0_queue(ep, req);
  366. else if (request && !ep->stall)
  367. enable_fifo_int(ep);
  368. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  369. return 0;
  370. }
  371. static int fusb300_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  372. {
  373. struct fusb300_ep *ep;
  374. struct fusb300_request *req;
  375. unsigned long flags;
  376. ep = container_of(_ep, struct fusb300_ep, ep);
  377. req = container_of(_req, struct fusb300_request, req);
  378. spin_lock_irqsave(&ep->fusb300->lock, flags);
  379. if (!list_empty(&ep->queue))
  380. done(ep, req, -ECONNRESET);
  381. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  382. return 0;
  383. }
  384. static int fusb300_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge)
  385. {
  386. struct fusb300_ep *ep;
  387. struct fusb300 *fusb300;
  388. unsigned long flags;
  389. int ret = 0;
  390. ep = container_of(_ep, struct fusb300_ep, ep);
  391. fusb300 = ep->fusb300;
  392. spin_lock_irqsave(&ep->fusb300->lock, flags);
  393. if (!list_empty(&ep->queue)) {
  394. ret = -EAGAIN;
  395. goto out;
  396. }
  397. if (value) {
  398. fusb300_set_epnstall(fusb300, ep->epnum);
  399. ep->stall = 1;
  400. if (wedge)
  401. ep->wedged = 1;
  402. } else {
  403. fusb300_clear_epnstall(fusb300, ep->epnum);
  404. ep->stall = 0;
  405. ep->wedged = 0;
  406. }
  407. out:
  408. spin_unlock_irqrestore(&ep->fusb300->lock, flags);
  409. return ret;
  410. }
  411. static int fusb300_set_halt(struct usb_ep *_ep, int value)
  412. {
  413. return fusb300_set_halt_and_wedge(_ep, value, 0);
  414. }
  415. static int fusb300_set_wedge(struct usb_ep *_ep)
  416. {
  417. return fusb300_set_halt_and_wedge(_ep, 1, 1);
  418. }
  419. static void fusb300_fifo_flush(struct usb_ep *_ep)
  420. {
  421. }
  422. static struct usb_ep_ops fusb300_ep_ops = {
  423. .enable = fusb300_enable,
  424. .disable = fusb300_disable,
  425. .alloc_request = fusb300_alloc_request,
  426. .free_request = fusb300_free_request,
  427. .queue = fusb300_queue,
  428. .dequeue = fusb300_dequeue,
  429. .set_halt = fusb300_set_halt,
  430. .fifo_flush = fusb300_fifo_flush,
  431. .set_wedge = fusb300_set_wedge,
  432. };
  433. /*****************************************************************************/
  434. static void fusb300_clear_int(struct fusb300 *fusb300, u32 offset,
  435. u32 value)
  436. {
  437. iowrite32(value, fusb300->reg + offset);
  438. }
  439. static void fusb300_reset(void)
  440. {
  441. }
  442. static void fusb300_set_cxstall(struct fusb300 *fusb300)
  443. {
  444. fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR,
  445. FUSB300_CSR_STL);
  446. }
  447. static void fusb300_set_cxdone(struct fusb300 *fusb300)
  448. {
  449. fusb300_enable_bit(fusb300, FUSB300_OFFSET_CSR,
  450. FUSB300_CSR_DONE);
  451. }
  452. /* read data from cx fifo */
  453. static void fusb300_rdcxf(struct fusb300 *fusb300,
  454. u8 *buffer, u32 length)
  455. {
  456. int i = 0;
  457. u8 *tmp;
  458. u32 data;
  459. tmp = buffer;
  460. for (i = (length >> 2); i > 0; i--) {
  461. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  462. printk(KERN_DEBUG " 0x%x\n", data);
  463. *tmp = data & 0xFF;
  464. *(tmp + 1) = (data >> 8) & 0xFF;
  465. *(tmp + 2) = (data >> 16) & 0xFF;
  466. *(tmp + 3) = (data >> 24) & 0xFF;
  467. tmp = tmp + 4;
  468. }
  469. switch (length % 4) {
  470. case 1:
  471. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  472. printk(KERN_DEBUG " 0x%x\n", data);
  473. *tmp = data & 0xFF;
  474. break;
  475. case 2:
  476. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  477. printk(KERN_DEBUG " 0x%x\n", data);
  478. *tmp = data & 0xFF;
  479. *(tmp + 1) = (data >> 8) & 0xFF;
  480. break;
  481. case 3:
  482. data = ioread32(fusb300->reg + FUSB300_OFFSET_CXPORT);
  483. printk(KERN_DEBUG " 0x%x\n", data);
  484. *tmp = data & 0xFF;
  485. *(tmp + 1) = (data >> 8) & 0xFF;
  486. *(tmp + 2) = (data >> 16) & 0xFF;
  487. break;
  488. default:
  489. break;
  490. }
  491. }
  492. static void fusb300_rdfifo(struct fusb300_ep *ep,
  493. struct fusb300_request *req,
  494. u32 length)
  495. {
  496. int i = 0;
  497. u8 *tmp;
  498. u32 data, reg;
  499. struct fusb300 *fusb300 = ep->fusb300;
  500. tmp = req->req.buf + req->req.actual;
  501. req->req.actual += length;
  502. if (req->req.actual > req->req.length)
  503. printk(KERN_DEBUG "req->req.actual > req->req.length\n");
  504. for (i = (length >> 2); i > 0; i--) {
  505. data = ioread32(fusb300->reg +
  506. FUSB300_OFFSET_EPPORT(ep->epnum));
  507. *tmp = data & 0xFF;
  508. *(tmp + 1) = (data >> 8) & 0xFF;
  509. *(tmp + 2) = (data >> 16) & 0xFF;
  510. *(tmp + 3) = (data >> 24) & 0xFF;
  511. tmp = tmp + 4;
  512. }
  513. switch (length % 4) {
  514. case 1:
  515. data = ioread32(fusb300->reg +
  516. FUSB300_OFFSET_EPPORT(ep->epnum));
  517. *tmp = data & 0xFF;
  518. break;
  519. case 2:
  520. data = ioread32(fusb300->reg +
  521. FUSB300_OFFSET_EPPORT(ep->epnum));
  522. *tmp = data & 0xFF;
  523. *(tmp + 1) = (data >> 8) & 0xFF;
  524. break;
  525. case 3:
  526. data = ioread32(fusb300->reg +
  527. FUSB300_OFFSET_EPPORT(ep->epnum));
  528. *tmp = data & 0xFF;
  529. *(tmp + 1) = (data >> 8) & 0xFF;
  530. *(tmp + 2) = (data >> 16) & 0xFF;
  531. break;
  532. default:
  533. break;
  534. }
  535. do {
  536. reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
  537. reg &= FUSB300_IGR1_SYNF0_EMPTY_INT;
  538. if (i)
  539. printk(KERN_INFO "sync fifo is not empty!\n");
  540. i++;
  541. } while (!reg);
  542. }
  543. static u8 fusb300_get_epnstall(struct fusb300 *fusb300, u8 ep)
  544. {
  545. u8 value;
  546. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
  547. value = reg & FUSB300_EPSET0_STL;
  548. return value;
  549. }
  550. static u8 fusb300_get_cxstall(struct fusb300 *fusb300)
  551. {
  552. u8 value;
  553. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_CSR);
  554. value = (reg & FUSB300_CSR_STL) >> 1;
  555. return value;
  556. }
  557. static void request_error(struct fusb300 *fusb300)
  558. {
  559. fusb300_set_cxstall(fusb300);
  560. printk(KERN_DEBUG "request error!!\n");
  561. }
  562. static void get_status(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  563. __releases(fusb300->lock)
  564. __acquires(fusb300->lock)
  565. {
  566. u8 ep;
  567. u16 status = 0;
  568. u16 w_index = ctrl->wIndex;
  569. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  570. case USB_RECIP_DEVICE:
  571. status = 1 << USB_DEVICE_SELF_POWERED;
  572. break;
  573. case USB_RECIP_INTERFACE:
  574. status = 0;
  575. break;
  576. case USB_RECIP_ENDPOINT:
  577. ep = w_index & USB_ENDPOINT_NUMBER_MASK;
  578. if (ep) {
  579. if (fusb300_get_epnstall(fusb300, ep))
  580. status = 1 << USB_ENDPOINT_HALT;
  581. } else {
  582. if (fusb300_get_cxstall(fusb300))
  583. status = 0;
  584. }
  585. break;
  586. default:
  587. request_error(fusb300);
  588. return; /* exit */
  589. }
  590. fusb300->ep0_data = cpu_to_le16(status);
  591. fusb300->ep0_req->buf = &fusb300->ep0_data;
  592. fusb300->ep0_req->length = 2;
  593. spin_unlock(&fusb300->lock);
  594. fusb300_queue(fusb300->gadget.ep0, fusb300->ep0_req, GFP_KERNEL);
  595. spin_lock(&fusb300->lock);
  596. }
  597. static void set_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  598. {
  599. u8 ep;
  600. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  601. case USB_RECIP_DEVICE:
  602. fusb300_set_cxdone(fusb300);
  603. break;
  604. case USB_RECIP_INTERFACE:
  605. fusb300_set_cxdone(fusb300);
  606. break;
  607. case USB_RECIP_ENDPOINT: {
  608. u16 w_index = le16_to_cpu(ctrl->wIndex);
  609. ep = w_index & USB_ENDPOINT_NUMBER_MASK;
  610. if (ep)
  611. fusb300_set_epnstall(fusb300, ep);
  612. else
  613. fusb300_set_cxstall(fusb300);
  614. fusb300_set_cxdone(fusb300);
  615. }
  616. break;
  617. default:
  618. request_error(fusb300);
  619. break;
  620. }
  621. }
  622. static void fusb300_clear_seqnum(struct fusb300 *fusb300, u8 ep)
  623. {
  624. fusb300_enable_bit(fusb300, FUSB300_OFFSET_EPSET0(ep),
  625. FUSB300_EPSET0_CLRSEQNUM);
  626. }
  627. static void clear_feature(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  628. {
  629. struct fusb300_ep *ep =
  630. fusb300->ep[ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK];
  631. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  632. case USB_RECIP_DEVICE:
  633. fusb300_set_cxdone(fusb300);
  634. break;
  635. case USB_RECIP_INTERFACE:
  636. fusb300_set_cxdone(fusb300);
  637. break;
  638. case USB_RECIP_ENDPOINT:
  639. if (ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK) {
  640. if (ep->wedged) {
  641. fusb300_set_cxdone(fusb300);
  642. break;
  643. }
  644. if (ep->stall) {
  645. ep->stall = 0;
  646. fusb300_clear_seqnum(fusb300, ep->epnum);
  647. fusb300_clear_epnstall(fusb300, ep->epnum);
  648. if (!list_empty(&ep->queue))
  649. enable_fifo_int(ep);
  650. }
  651. }
  652. fusb300_set_cxdone(fusb300);
  653. break;
  654. default:
  655. request_error(fusb300);
  656. break;
  657. }
  658. }
  659. static void fusb300_set_dev_addr(struct fusb300 *fusb300, u16 addr)
  660. {
  661. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_DAR);
  662. reg &= ~FUSB300_DAR_DRVADDR_MSK;
  663. reg |= FUSB300_DAR_DRVADDR(addr);
  664. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_DAR);
  665. }
  666. static void set_address(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  667. {
  668. if (ctrl->wValue >= 0x0100)
  669. request_error(fusb300);
  670. else {
  671. fusb300_set_dev_addr(fusb300, ctrl->wValue);
  672. fusb300_set_cxdone(fusb300);
  673. }
  674. }
  675. #define UVC_COPY_DESCRIPTORS(mem, src) \
  676. do { \
  677. const struct usb_descriptor_header * const *__src; \
  678. for (__src = src; *__src; ++__src) { \
  679. memcpy(mem, *__src, (*__src)->bLength); \
  680. mem += (*__src)->bLength; \
  681. } \
  682. } while (0)
  683. static int setup_packet(struct fusb300 *fusb300, struct usb_ctrlrequest *ctrl)
  684. {
  685. u8 *p = (u8 *)ctrl;
  686. u8 ret = 0;
  687. u8 i = 0;
  688. fusb300_rdcxf(fusb300, p, 8);
  689. fusb300->ep0_dir = ctrl->bRequestType & USB_DIR_IN;
  690. fusb300->ep0_length = ctrl->wLength;
  691. /* check request */
  692. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  693. switch (ctrl->bRequest) {
  694. case USB_REQ_GET_STATUS:
  695. get_status(fusb300, ctrl);
  696. break;
  697. case USB_REQ_CLEAR_FEATURE:
  698. clear_feature(fusb300, ctrl);
  699. break;
  700. case USB_REQ_SET_FEATURE:
  701. set_feature(fusb300, ctrl);
  702. break;
  703. case USB_REQ_SET_ADDRESS:
  704. set_address(fusb300, ctrl);
  705. break;
  706. case USB_REQ_SET_CONFIGURATION:
  707. fusb300_enable_bit(fusb300, FUSB300_OFFSET_DAR,
  708. FUSB300_DAR_SETCONFG);
  709. /* clear sequence number */
  710. for (i = 1; i <= FUSB300_MAX_NUM_EP; i++)
  711. fusb300_clear_seqnum(fusb300, i);
  712. fusb300->reenum = 1;
  713. ret = 1;
  714. break;
  715. default:
  716. ret = 1;
  717. break;
  718. }
  719. } else
  720. ret = 1;
  721. return ret;
  722. }
  723. static void done(struct fusb300_ep *ep, struct fusb300_request *req,
  724. int status)
  725. {
  726. list_del_init(&req->queue);
  727. /* don't modify queue heads during completion callback */
  728. if (ep->fusb300->gadget.speed == USB_SPEED_UNKNOWN)
  729. req->req.status = -ESHUTDOWN;
  730. else
  731. req->req.status = status;
  732. spin_unlock(&ep->fusb300->lock);
  733. usb_gadget_giveback_request(&ep->ep, &req->req);
  734. spin_lock(&ep->fusb300->lock);
  735. if (ep->epnum) {
  736. disable_fifo_int(ep);
  737. if (!list_empty(&ep->queue))
  738. enable_fifo_int(ep);
  739. } else
  740. fusb300_set_cxdone(ep->fusb300);
  741. }
  742. static void fusb300_fill_idma_prdtbl(struct fusb300_ep *ep, dma_addr_t d,
  743. u32 len)
  744. {
  745. u32 value;
  746. u32 reg;
  747. /* wait SW owner */
  748. do {
  749. reg = ioread32(ep->fusb300->reg +
  750. FUSB300_OFFSET_EPPRD_W0(ep->epnum));
  751. reg &= FUSB300_EPPRD0_H;
  752. } while (reg);
  753. iowrite32(d, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W1(ep->epnum));
  754. value = FUSB300_EPPRD0_BTC(len) | FUSB300_EPPRD0_H |
  755. FUSB300_EPPRD0_F | FUSB300_EPPRD0_L | FUSB300_EPPRD0_I;
  756. iowrite32(value, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W0(ep->epnum));
  757. iowrite32(0x0, ep->fusb300->reg + FUSB300_OFFSET_EPPRD_W2(ep->epnum));
  758. fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_EPPRDRDY,
  759. FUSB300_EPPRDR_EP_PRD_RDY(ep->epnum));
  760. }
  761. static void fusb300_wait_idma_finished(struct fusb300_ep *ep)
  762. {
  763. u32 reg;
  764. do {
  765. reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR1);
  766. if ((reg & FUSB300_IGR1_VBUS_CHG_INT) ||
  767. (reg & FUSB300_IGR1_WARM_RST_INT) ||
  768. (reg & FUSB300_IGR1_HOT_RST_INT) ||
  769. (reg & FUSB300_IGR1_USBRST_INT)
  770. )
  771. goto IDMA_RESET;
  772. reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGR0);
  773. reg &= FUSB300_IGR0_EPn_PRD_INT(ep->epnum);
  774. } while (!reg);
  775. fusb300_clear_int(ep->fusb300, FUSB300_OFFSET_IGR0,
  776. FUSB300_IGR0_EPn_PRD_INT(ep->epnum));
  777. return;
  778. IDMA_RESET:
  779. reg = ioread32(ep->fusb300->reg + FUSB300_OFFSET_IGER0);
  780. reg &= ~FUSB300_IGER0_EEPn_PRD_INT(ep->epnum);
  781. iowrite32(reg, ep->fusb300->reg + FUSB300_OFFSET_IGER0);
  782. }
  783. static void fusb300_set_idma(struct fusb300_ep *ep,
  784. struct fusb300_request *req)
  785. {
  786. int ret;
  787. ret = usb_gadget_map_request(&ep->fusb300->gadget,
  788. &req->req, DMA_TO_DEVICE);
  789. if (ret)
  790. return;
  791. fusb300_enable_bit(ep->fusb300, FUSB300_OFFSET_IGER0,
  792. FUSB300_IGER0_EEPn_PRD_INT(ep->epnum));
  793. fusb300_fill_idma_prdtbl(ep, req->req.dma, req->req.length);
  794. /* check idma is done */
  795. fusb300_wait_idma_finished(ep);
  796. usb_gadget_unmap_request(&ep->fusb300->gadget,
  797. &req->req, DMA_TO_DEVICE);
  798. }
  799. static void in_ep_fifo_handler(struct fusb300_ep *ep)
  800. {
  801. struct fusb300_request *req = list_entry(ep->queue.next,
  802. struct fusb300_request, queue);
  803. if (req->req.length)
  804. fusb300_set_idma(ep, req);
  805. done(ep, req, 0);
  806. }
  807. static void out_ep_fifo_handler(struct fusb300_ep *ep)
  808. {
  809. struct fusb300 *fusb300 = ep->fusb300;
  810. struct fusb300_request *req = list_entry(ep->queue.next,
  811. struct fusb300_request, queue);
  812. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_EPFFR(ep->epnum));
  813. u32 length = reg & FUSB300_FFR_BYCNT;
  814. fusb300_rdfifo(ep, req, length);
  815. /* finish out transfer */
  816. if ((req->req.length == req->req.actual) || (length < ep->ep.maxpacket))
  817. done(ep, req, 0);
  818. }
  819. static void check_device_mode(struct fusb300 *fusb300)
  820. {
  821. u32 reg = ioread32(fusb300->reg + FUSB300_OFFSET_GCR);
  822. switch (reg & FUSB300_GCR_DEVEN_MSK) {
  823. case FUSB300_GCR_DEVEN_SS:
  824. fusb300->gadget.speed = USB_SPEED_SUPER;
  825. break;
  826. case FUSB300_GCR_DEVEN_HS:
  827. fusb300->gadget.speed = USB_SPEED_HIGH;
  828. break;
  829. case FUSB300_GCR_DEVEN_FS:
  830. fusb300->gadget.speed = USB_SPEED_FULL;
  831. break;
  832. default:
  833. fusb300->gadget.speed = USB_SPEED_UNKNOWN;
  834. break;
  835. }
  836. printk(KERN_INFO "dev_mode = %d\n", (reg & FUSB300_GCR_DEVEN_MSK));
  837. }
  838. static void fusb300_ep0out(struct fusb300 *fusb300)
  839. {
  840. struct fusb300_ep *ep = fusb300->ep[0];
  841. u32 reg;
  842. if (!list_empty(&ep->queue)) {
  843. struct fusb300_request *req;
  844. req = list_first_entry(&ep->queue,
  845. struct fusb300_request, queue);
  846. if (req->req.length)
  847. fusb300_rdcxf(ep->fusb300, req->req.buf,
  848. req->req.length);
  849. done(ep, req, 0);
  850. reg = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1);
  851. reg &= ~FUSB300_IGER1_CX_OUT_INT;
  852. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_IGER1);
  853. } else
  854. pr_err("%s : empty queue\n", __func__);
  855. }
  856. static void fusb300_ep0in(struct fusb300 *fusb300)
  857. {
  858. struct fusb300_request *req;
  859. struct fusb300_ep *ep = fusb300->ep[0];
  860. if ((!list_empty(&ep->queue)) && (fusb300->ep0_dir)) {
  861. req = list_entry(ep->queue.next,
  862. struct fusb300_request, queue);
  863. if (req->req.length)
  864. fusb300_wrcxf(ep, req);
  865. if ((req->req.length - req->req.actual) < ep->ep.maxpacket)
  866. done(ep, req, 0);
  867. } else
  868. fusb300_set_cxdone(fusb300);
  869. }
  870. static void fusb300_grp2_handler(void)
  871. {
  872. }
  873. static void fusb300_grp3_handler(void)
  874. {
  875. }
  876. static void fusb300_grp4_handler(void)
  877. {
  878. }
  879. static void fusb300_grp5_handler(void)
  880. {
  881. }
  882. static irqreturn_t fusb300_irq(int irq, void *_fusb300)
  883. {
  884. struct fusb300 *fusb300 = _fusb300;
  885. u32 int_grp1 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR1);
  886. u32 int_grp1_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER1);
  887. u32 int_grp0 = ioread32(fusb300->reg + FUSB300_OFFSET_IGR0);
  888. u32 int_grp0_en = ioread32(fusb300->reg + FUSB300_OFFSET_IGER0);
  889. struct usb_ctrlrequest ctrl;
  890. u8 in;
  891. u32 reg;
  892. int i;
  893. spin_lock(&fusb300->lock);
  894. int_grp1 &= int_grp1_en;
  895. int_grp0 &= int_grp0_en;
  896. if (int_grp1 & FUSB300_IGR1_WARM_RST_INT) {
  897. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  898. FUSB300_IGR1_WARM_RST_INT);
  899. printk(KERN_INFO"fusb300_warmreset\n");
  900. fusb300_reset();
  901. }
  902. if (int_grp1 & FUSB300_IGR1_HOT_RST_INT) {
  903. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  904. FUSB300_IGR1_HOT_RST_INT);
  905. printk(KERN_INFO"fusb300_hotreset\n");
  906. fusb300_reset();
  907. }
  908. if (int_grp1 & FUSB300_IGR1_USBRST_INT) {
  909. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  910. FUSB300_IGR1_USBRST_INT);
  911. fusb300_reset();
  912. }
  913. /* COMABT_INT has a highest priority */
  914. if (int_grp1 & FUSB300_IGR1_CX_COMABT_INT) {
  915. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  916. FUSB300_IGR1_CX_COMABT_INT);
  917. printk(KERN_INFO"fusb300_ep0abt\n");
  918. }
  919. if (int_grp1 & FUSB300_IGR1_VBUS_CHG_INT) {
  920. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  921. FUSB300_IGR1_VBUS_CHG_INT);
  922. printk(KERN_INFO"fusb300_vbus_change\n");
  923. }
  924. if (int_grp1 & FUSB300_IGR1_U3_EXIT_FAIL_INT) {
  925. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  926. FUSB300_IGR1_U3_EXIT_FAIL_INT);
  927. }
  928. if (int_grp1 & FUSB300_IGR1_U2_EXIT_FAIL_INT) {
  929. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  930. FUSB300_IGR1_U2_EXIT_FAIL_INT);
  931. }
  932. if (int_grp1 & FUSB300_IGR1_U1_EXIT_FAIL_INT) {
  933. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  934. FUSB300_IGR1_U1_EXIT_FAIL_INT);
  935. }
  936. if (int_grp1 & FUSB300_IGR1_U2_ENTRY_FAIL_INT) {
  937. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  938. FUSB300_IGR1_U2_ENTRY_FAIL_INT);
  939. }
  940. if (int_grp1 & FUSB300_IGR1_U1_ENTRY_FAIL_INT) {
  941. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  942. FUSB300_IGR1_U1_ENTRY_FAIL_INT);
  943. }
  944. if (int_grp1 & FUSB300_IGR1_U3_EXIT_INT) {
  945. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  946. FUSB300_IGR1_U3_EXIT_INT);
  947. printk(KERN_INFO "FUSB300_IGR1_U3_EXIT_INT\n");
  948. }
  949. if (int_grp1 & FUSB300_IGR1_U2_EXIT_INT) {
  950. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  951. FUSB300_IGR1_U2_EXIT_INT);
  952. printk(KERN_INFO "FUSB300_IGR1_U2_EXIT_INT\n");
  953. }
  954. if (int_grp1 & FUSB300_IGR1_U1_EXIT_INT) {
  955. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  956. FUSB300_IGR1_U1_EXIT_INT);
  957. printk(KERN_INFO "FUSB300_IGR1_U1_EXIT_INT\n");
  958. }
  959. if (int_grp1 & FUSB300_IGR1_U3_ENTRY_INT) {
  960. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  961. FUSB300_IGR1_U3_ENTRY_INT);
  962. printk(KERN_INFO "FUSB300_IGR1_U3_ENTRY_INT\n");
  963. fusb300_enable_bit(fusb300, FUSB300_OFFSET_SSCR1,
  964. FUSB300_SSCR1_GO_U3_DONE);
  965. }
  966. if (int_grp1 & FUSB300_IGR1_U2_ENTRY_INT) {
  967. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  968. FUSB300_IGR1_U2_ENTRY_INT);
  969. printk(KERN_INFO "FUSB300_IGR1_U2_ENTRY_INT\n");
  970. }
  971. if (int_grp1 & FUSB300_IGR1_U1_ENTRY_INT) {
  972. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  973. FUSB300_IGR1_U1_ENTRY_INT);
  974. printk(KERN_INFO "FUSB300_IGR1_U1_ENTRY_INT\n");
  975. }
  976. if (int_grp1 & FUSB300_IGR1_RESM_INT) {
  977. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  978. FUSB300_IGR1_RESM_INT);
  979. printk(KERN_INFO "fusb300_resume\n");
  980. }
  981. if (int_grp1 & FUSB300_IGR1_SUSP_INT) {
  982. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  983. FUSB300_IGR1_SUSP_INT);
  984. printk(KERN_INFO "fusb300_suspend\n");
  985. }
  986. if (int_grp1 & FUSB300_IGR1_HS_LPM_INT) {
  987. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  988. FUSB300_IGR1_HS_LPM_INT);
  989. printk(KERN_INFO "fusb300_HS_LPM_INT\n");
  990. }
  991. if (int_grp1 & FUSB300_IGR1_DEV_MODE_CHG_INT) {
  992. fusb300_clear_int(fusb300, FUSB300_OFFSET_IGR1,
  993. FUSB300_IGR1_DEV_MODE_CHG_INT);
  994. check_device_mode(fusb300);
  995. }
  996. if (int_grp1 & FUSB300_IGR1_CX_COMFAIL_INT) {
  997. fusb300_set_cxstall(fusb300);
  998. printk(KERN_INFO "fusb300_ep0fail\n");
  999. }
  1000. if (int_grp1 & FUSB300_IGR1_CX_SETUP_INT) {
  1001. printk(KERN_INFO "fusb300_ep0setup\n");
  1002. if (setup_packet(fusb300, &ctrl)) {
  1003. spin_unlock(&fusb300->lock);
  1004. if (fusb300->driver->setup(&fusb300->gadget, &ctrl) < 0)
  1005. fusb300_set_cxstall(fusb300);
  1006. spin_lock(&fusb300->lock);
  1007. }
  1008. }
  1009. if (int_grp1 & FUSB300_IGR1_CX_CMDEND_INT)
  1010. printk(KERN_INFO "fusb300_cmdend\n");
  1011. if (int_grp1 & FUSB300_IGR1_CX_OUT_INT) {
  1012. printk(KERN_INFO "fusb300_cxout\n");
  1013. fusb300_ep0out(fusb300);
  1014. }
  1015. if (int_grp1 & FUSB300_IGR1_CX_IN_INT) {
  1016. printk(KERN_INFO "fusb300_cxin\n");
  1017. fusb300_ep0in(fusb300);
  1018. }
  1019. if (int_grp1 & FUSB300_IGR1_INTGRP5)
  1020. fusb300_grp5_handler();
  1021. if (int_grp1 & FUSB300_IGR1_INTGRP4)
  1022. fusb300_grp4_handler();
  1023. if (int_grp1 & FUSB300_IGR1_INTGRP3)
  1024. fusb300_grp3_handler();
  1025. if (int_grp1 & FUSB300_IGR1_INTGRP2)
  1026. fusb300_grp2_handler();
  1027. if (int_grp0) {
  1028. for (i = 1; i < FUSB300_MAX_NUM_EP; i++) {
  1029. if (int_grp0 & FUSB300_IGR0_EPn_FIFO_INT(i)) {
  1030. reg = ioread32(fusb300->reg +
  1031. FUSB300_OFFSET_EPSET1(i));
  1032. in = (reg & FUSB300_EPSET1_DIRIN) ? 1 : 0;
  1033. if (in)
  1034. in_ep_fifo_handler(fusb300->ep[i]);
  1035. else
  1036. out_ep_fifo_handler(fusb300->ep[i]);
  1037. }
  1038. }
  1039. }
  1040. spin_unlock(&fusb300->lock);
  1041. return IRQ_HANDLED;
  1042. }
  1043. static void fusb300_set_u2_timeout(struct fusb300 *fusb300,
  1044. u32 time)
  1045. {
  1046. u32 reg;
  1047. reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT);
  1048. reg &= ~0xff;
  1049. reg |= FUSB300_SSCR2_U2TIMEOUT(time);
  1050. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT);
  1051. }
  1052. static void fusb300_set_u1_timeout(struct fusb300 *fusb300,
  1053. u32 time)
  1054. {
  1055. u32 reg;
  1056. reg = ioread32(fusb300->reg + FUSB300_OFFSET_TT);
  1057. reg &= ~(0xff << 8);
  1058. reg |= FUSB300_SSCR2_U1TIMEOUT(time);
  1059. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_TT);
  1060. }
  1061. static void init_controller(struct fusb300 *fusb300)
  1062. {
  1063. u32 reg;
  1064. u32 mask = 0;
  1065. u32 val = 0;
  1066. /* split on */
  1067. mask = val = FUSB300_AHBBCR_S0_SPLIT_ON | FUSB300_AHBBCR_S1_SPLIT_ON;
  1068. reg = ioread32(fusb300->reg + FUSB300_OFFSET_AHBCR);
  1069. reg &= ~mask;
  1070. reg |= val;
  1071. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_AHBCR);
  1072. /* enable high-speed LPM */
  1073. mask = val = FUSB300_HSCR_HS_LPM_PERMIT;
  1074. reg = ioread32(fusb300->reg + FUSB300_OFFSET_HSCR);
  1075. reg &= ~mask;
  1076. reg |= val;
  1077. iowrite32(reg, fusb300->reg + FUSB300_OFFSET_HSCR);
  1078. /*set u1 u2 timmer*/
  1079. fusb300_set_u2_timeout(fusb300, 0xff);
  1080. fusb300_set_u1_timeout(fusb300, 0xff);
  1081. /* enable all grp1 interrupt */
  1082. iowrite32(0xcfffff9f, fusb300->reg + FUSB300_OFFSET_IGER1);
  1083. }
  1084. /*------------------------------------------------------------------------*/
  1085. static int fusb300_udc_start(struct usb_gadget *g,
  1086. struct usb_gadget_driver *driver)
  1087. {
  1088. struct fusb300 *fusb300 = to_fusb300(g);
  1089. /* hook up the driver */
  1090. driver->driver.bus = NULL;
  1091. fusb300->driver = driver;
  1092. return 0;
  1093. }
  1094. static int fusb300_udc_stop(struct usb_gadget *g)
  1095. {
  1096. struct fusb300 *fusb300 = to_fusb300(g);
  1097. init_controller(fusb300);
  1098. fusb300->driver = NULL;
  1099. return 0;
  1100. }
  1101. /*--------------------------------------------------------------------------*/
  1102. static int fusb300_udc_pullup(struct usb_gadget *_gadget, int is_active)
  1103. {
  1104. return 0;
  1105. }
  1106. static const struct usb_gadget_ops fusb300_gadget_ops = {
  1107. .pullup = fusb300_udc_pullup,
  1108. .udc_start = fusb300_udc_start,
  1109. .udc_stop = fusb300_udc_stop,
  1110. };
  1111. static int fusb300_remove(struct platform_device *pdev)
  1112. {
  1113. struct fusb300 *fusb300 = platform_get_drvdata(pdev);
  1114. usb_del_gadget_udc(&fusb300->gadget);
  1115. iounmap(fusb300->reg);
  1116. free_irq(platform_get_irq(pdev, 0), fusb300);
  1117. fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req);
  1118. kfree(fusb300);
  1119. return 0;
  1120. }
  1121. static int fusb300_probe(struct platform_device *pdev)
  1122. {
  1123. struct resource *res, *ires, *ires1;
  1124. void __iomem *reg = NULL;
  1125. struct fusb300 *fusb300 = NULL;
  1126. struct fusb300_ep *_ep[FUSB300_MAX_NUM_EP];
  1127. int ret = 0;
  1128. int i;
  1129. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1130. if (!res) {
  1131. ret = -ENODEV;
  1132. pr_err("platform_get_resource error.\n");
  1133. goto clean_up;
  1134. }
  1135. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1136. if (!ires) {
  1137. ret = -ENODEV;
  1138. dev_err(&pdev->dev,
  1139. "platform_get_resource IORESOURCE_IRQ error.\n");
  1140. goto clean_up;
  1141. }
  1142. ires1 = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
  1143. if (!ires1) {
  1144. ret = -ENODEV;
  1145. dev_err(&pdev->dev,
  1146. "platform_get_resource IORESOURCE_IRQ 1 error.\n");
  1147. goto clean_up;
  1148. }
  1149. reg = ioremap(res->start, resource_size(res));
  1150. if (reg == NULL) {
  1151. ret = -ENOMEM;
  1152. pr_err("ioremap error.\n");
  1153. goto clean_up;
  1154. }
  1155. /* initialize udc */
  1156. fusb300 = kzalloc(sizeof(struct fusb300), GFP_KERNEL);
  1157. if (fusb300 == NULL) {
  1158. ret = -ENOMEM;
  1159. goto clean_up;
  1160. }
  1161. for (i = 0; i < FUSB300_MAX_NUM_EP; i++) {
  1162. _ep[i] = kzalloc(sizeof(struct fusb300_ep), GFP_KERNEL);
  1163. if (_ep[i] == NULL) {
  1164. ret = -ENOMEM;
  1165. goto clean_up;
  1166. }
  1167. fusb300->ep[i] = _ep[i];
  1168. }
  1169. spin_lock_init(&fusb300->lock);
  1170. platform_set_drvdata(pdev, fusb300);
  1171. fusb300->gadget.ops = &fusb300_gadget_ops;
  1172. fusb300->gadget.max_speed = USB_SPEED_HIGH;
  1173. fusb300->gadget.name = udc_name;
  1174. fusb300->reg = reg;
  1175. ret = request_irq(ires->start, fusb300_irq, IRQF_SHARED,
  1176. udc_name, fusb300);
  1177. if (ret < 0) {
  1178. pr_err("request_irq error (%d)\n", ret);
  1179. goto clean_up;
  1180. }
  1181. ret = request_irq(ires1->start, fusb300_irq,
  1182. IRQF_SHARED, udc_name, fusb300);
  1183. if (ret < 0) {
  1184. pr_err("request_irq1 error (%d)\n", ret);
  1185. goto clean_up;
  1186. }
  1187. INIT_LIST_HEAD(&fusb300->gadget.ep_list);
  1188. for (i = 0; i < FUSB300_MAX_NUM_EP ; i++) {
  1189. struct fusb300_ep *ep = fusb300->ep[i];
  1190. if (i != 0) {
  1191. INIT_LIST_HEAD(&fusb300->ep[i]->ep.ep_list);
  1192. list_add_tail(&fusb300->ep[i]->ep.ep_list,
  1193. &fusb300->gadget.ep_list);
  1194. }
  1195. ep->fusb300 = fusb300;
  1196. INIT_LIST_HEAD(&ep->queue);
  1197. ep->ep.name = fusb300_ep_name[i];
  1198. ep->ep.ops = &fusb300_ep_ops;
  1199. usb_ep_set_maxpacket_limit(&ep->ep, HS_BULK_MAX_PACKET_SIZE);
  1200. if (i == 0) {
  1201. ep->ep.caps.type_control = true;
  1202. } else {
  1203. ep->ep.caps.type_iso = true;
  1204. ep->ep.caps.type_bulk = true;
  1205. ep->ep.caps.type_int = true;
  1206. }
  1207. ep->ep.caps.dir_in = true;
  1208. ep->ep.caps.dir_out = true;
  1209. }
  1210. usb_ep_set_maxpacket_limit(&fusb300->ep[0]->ep, HS_CTL_MAX_PACKET_SIZE);
  1211. fusb300->ep[0]->epnum = 0;
  1212. fusb300->gadget.ep0 = &fusb300->ep[0]->ep;
  1213. INIT_LIST_HEAD(&fusb300->gadget.ep0->ep_list);
  1214. fusb300->ep0_req = fusb300_alloc_request(&fusb300->ep[0]->ep,
  1215. GFP_KERNEL);
  1216. if (fusb300->ep0_req == NULL) {
  1217. ret = -ENOMEM;
  1218. goto clean_up3;
  1219. }
  1220. init_controller(fusb300);
  1221. ret = usb_add_gadget_udc(&pdev->dev, &fusb300->gadget);
  1222. if (ret)
  1223. goto err_add_udc;
  1224. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1225. return 0;
  1226. err_add_udc:
  1227. fusb300_free_request(&fusb300->ep[0]->ep, fusb300->ep0_req);
  1228. clean_up3:
  1229. free_irq(ires->start, fusb300);
  1230. clean_up:
  1231. if (fusb300) {
  1232. if (fusb300->ep0_req)
  1233. fusb300_free_request(&fusb300->ep[0]->ep,
  1234. fusb300->ep0_req);
  1235. kfree(fusb300);
  1236. }
  1237. if (reg)
  1238. iounmap(reg);
  1239. return ret;
  1240. }
  1241. static struct platform_driver fusb300_driver = {
  1242. .remove = fusb300_remove,
  1243. .driver = {
  1244. .name = (char *) udc_name,
  1245. },
  1246. };
  1247. module_platform_driver_probe(fusb300_driver, fusb300_probe);