m66592-udc.c 42 KB

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  1. /*
  2. * M66592 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2007 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/delay.h>
  15. #include <linux/io.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/err.h>
  19. #include <linux/usb/ch9.h>
  20. #include <linux/usb/gadget.h>
  21. #include "m66592-udc.h"
  22. MODULE_DESCRIPTION("M66592 USB gadget driver");
  23. MODULE_LICENSE("GPL");
  24. MODULE_AUTHOR("Yoshihiro Shimoda");
  25. MODULE_ALIAS("platform:m66592_udc");
  26. #define DRIVER_VERSION "21 July 2009"
  27. static const char udc_name[] = "m66592_udc";
  28. static const char *m66592_ep_name[] = {
  29. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
  30. };
  31. static void disable_controller(struct m66592 *m66592);
  32. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
  33. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
  34. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  35. gfp_t gfp_flags);
  36. static void transfer_complete(struct m66592_ep *ep,
  37. struct m66592_request *req, int status);
  38. /*-------------------------------------------------------------------------*/
  39. static inline u16 get_usb_speed(struct m66592 *m66592)
  40. {
  41. return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
  42. }
  43. static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  44. unsigned long reg)
  45. {
  46. u16 tmp;
  47. tmp = m66592_read(m66592, M66592_INTENB0);
  48. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  49. M66592_INTENB0);
  50. m66592_bset(m66592, (1 << pipenum), reg);
  51. m66592_write(m66592, tmp, M66592_INTENB0);
  52. }
  53. static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  54. unsigned long reg)
  55. {
  56. u16 tmp;
  57. tmp = m66592_read(m66592, M66592_INTENB0);
  58. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  59. M66592_INTENB0);
  60. m66592_bclr(m66592, (1 << pipenum), reg);
  61. m66592_write(m66592, tmp, M66592_INTENB0);
  62. }
  63. static void m66592_usb_connect(struct m66592 *m66592)
  64. {
  65. m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
  66. m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  67. M66592_INTENB0);
  68. m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  69. m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
  70. }
  71. static void m66592_usb_disconnect(struct m66592 *m66592)
  72. __releases(m66592->lock)
  73. __acquires(m66592->lock)
  74. {
  75. m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
  76. m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  77. M66592_INTENB0);
  78. m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  79. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  80. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  81. spin_unlock(&m66592->lock);
  82. m66592->driver->disconnect(&m66592->gadget);
  83. spin_lock(&m66592->lock);
  84. disable_controller(m66592);
  85. INIT_LIST_HEAD(&m66592->ep[0].queue);
  86. }
  87. static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
  88. {
  89. u16 pid = 0;
  90. unsigned long offset;
  91. if (pipenum == 0)
  92. pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
  93. else if (pipenum < M66592_MAX_NUM_PIPE) {
  94. offset = get_pipectr_addr(pipenum);
  95. pid = m66592_read(m66592, offset) & M66592_PID;
  96. } else
  97. pr_err("unexpect pipe num (%d)\n", pipenum);
  98. return pid;
  99. }
  100. static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
  101. u16 pid)
  102. {
  103. unsigned long offset;
  104. if (pipenum == 0)
  105. m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
  106. else if (pipenum < M66592_MAX_NUM_PIPE) {
  107. offset = get_pipectr_addr(pipenum);
  108. m66592_mdfy(m66592, pid, M66592_PID, offset);
  109. } else
  110. pr_err("unexpect pipe num (%d)\n", pipenum);
  111. }
  112. static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
  113. {
  114. control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
  115. }
  116. static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
  117. {
  118. control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
  119. }
  120. static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
  121. {
  122. control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
  123. }
  124. static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
  125. {
  126. u16 ret = 0;
  127. unsigned long offset;
  128. if (pipenum == 0)
  129. ret = m66592_read(m66592, M66592_DCPCTR);
  130. else if (pipenum < M66592_MAX_NUM_PIPE) {
  131. offset = get_pipectr_addr(pipenum);
  132. ret = m66592_read(m66592, offset);
  133. } else
  134. pr_err("unexpect pipe num (%d)\n", pipenum);
  135. return ret;
  136. }
  137. static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
  138. {
  139. unsigned long offset;
  140. pipe_stop(m66592, pipenum);
  141. if (pipenum == 0)
  142. m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
  143. else if (pipenum < M66592_MAX_NUM_PIPE) {
  144. offset = get_pipectr_addr(pipenum);
  145. m66592_bset(m66592, M66592_SQCLR, offset);
  146. } else
  147. pr_err("unexpect pipe num(%d)\n", pipenum);
  148. }
  149. static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
  150. {
  151. u16 tmp;
  152. int size;
  153. if (pipenum == 0) {
  154. tmp = m66592_read(m66592, M66592_DCPCFG);
  155. if ((tmp & M66592_CNTMD) != 0)
  156. size = 256;
  157. else {
  158. tmp = m66592_read(m66592, M66592_DCPMAXP);
  159. size = tmp & M66592_MAXP;
  160. }
  161. } else {
  162. m66592_write(m66592, pipenum, M66592_PIPESEL);
  163. tmp = m66592_read(m66592, M66592_PIPECFG);
  164. if ((tmp & M66592_CNTMD) != 0) {
  165. tmp = m66592_read(m66592, M66592_PIPEBUF);
  166. size = ((tmp >> 10) + 1) * 64;
  167. } else {
  168. tmp = m66592_read(m66592, M66592_PIPEMAXP);
  169. size = tmp & M66592_MXPS;
  170. }
  171. }
  172. return size;
  173. }
  174. static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
  175. {
  176. struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
  177. unsigned short mbw;
  178. if (ep->use_dma)
  179. return;
  180. m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
  181. ndelay(450);
  182. if (m66592->pdata->on_chip)
  183. mbw = M66592_MBW_32;
  184. else
  185. mbw = M66592_MBW_16;
  186. m66592_bset(m66592, mbw, ep->fifosel);
  187. }
  188. static int pipe_buffer_setting(struct m66592 *m66592,
  189. struct m66592_pipe_info *info)
  190. {
  191. u16 bufnum = 0, buf_bsize = 0;
  192. u16 pipecfg = 0;
  193. if (info->pipe == 0)
  194. return -EINVAL;
  195. m66592_write(m66592, info->pipe, M66592_PIPESEL);
  196. if (info->dir_in)
  197. pipecfg |= M66592_DIR;
  198. pipecfg |= info->type;
  199. pipecfg |= info->epnum;
  200. switch (info->type) {
  201. case M66592_INT:
  202. bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
  203. buf_bsize = 0;
  204. break;
  205. case M66592_BULK:
  206. /* isochronous pipes may be used as bulk pipes */
  207. if (info->pipe >= M66592_BASE_PIPENUM_BULK)
  208. bufnum = info->pipe - M66592_BASE_PIPENUM_BULK;
  209. else
  210. bufnum = info->pipe - M66592_BASE_PIPENUM_ISOC;
  211. bufnum = M66592_BASE_BUFNUM + (bufnum * 16);
  212. buf_bsize = 7;
  213. pipecfg |= M66592_DBLB;
  214. if (!info->dir_in)
  215. pipecfg |= M66592_SHTNAK;
  216. break;
  217. case M66592_ISO:
  218. bufnum = M66592_BASE_BUFNUM +
  219. (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
  220. buf_bsize = 7;
  221. break;
  222. }
  223. if (buf_bsize && ((bufnum + 16) >= M66592_MAX_BUFNUM)) {
  224. pr_err("m66592 pipe memory is insufficient\n");
  225. return -ENOMEM;
  226. }
  227. m66592_write(m66592, pipecfg, M66592_PIPECFG);
  228. m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
  229. m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
  230. if (info->interval)
  231. info->interval--;
  232. m66592_write(m66592, info->interval, M66592_PIPEPERI);
  233. return 0;
  234. }
  235. static void pipe_buffer_release(struct m66592 *m66592,
  236. struct m66592_pipe_info *info)
  237. {
  238. if (info->pipe == 0)
  239. return;
  240. if (is_bulk_pipe(info->pipe)) {
  241. m66592->bulk--;
  242. } else if (is_interrupt_pipe(info->pipe))
  243. m66592->interrupt--;
  244. else if (is_isoc_pipe(info->pipe)) {
  245. m66592->isochronous--;
  246. if (info->type == M66592_BULK)
  247. m66592->bulk--;
  248. } else
  249. pr_err("ep_release: unexpect pipenum (%d)\n",
  250. info->pipe);
  251. }
  252. static void pipe_initialize(struct m66592_ep *ep)
  253. {
  254. struct m66592 *m66592 = ep->m66592;
  255. unsigned short mbw;
  256. m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
  257. m66592_write(m66592, M66592_ACLRM, ep->pipectr);
  258. m66592_write(m66592, 0, ep->pipectr);
  259. m66592_write(m66592, M66592_SQCLR, ep->pipectr);
  260. if (ep->use_dma) {
  261. m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
  262. ndelay(450);
  263. if (m66592->pdata->on_chip)
  264. mbw = M66592_MBW_32;
  265. else
  266. mbw = M66592_MBW_16;
  267. m66592_bset(m66592, mbw, ep->fifosel);
  268. }
  269. }
  270. static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
  271. const struct usb_endpoint_descriptor *desc,
  272. u16 pipenum, int dma)
  273. {
  274. if ((pipenum != 0) && dma) {
  275. if (m66592->num_dma == 0) {
  276. m66592->num_dma++;
  277. ep->use_dma = 1;
  278. ep->fifoaddr = M66592_D0FIFO;
  279. ep->fifosel = M66592_D0FIFOSEL;
  280. ep->fifoctr = M66592_D0FIFOCTR;
  281. ep->fifotrn = M66592_D0FIFOTRN;
  282. } else if (!m66592->pdata->on_chip && m66592->num_dma == 1) {
  283. m66592->num_dma++;
  284. ep->use_dma = 1;
  285. ep->fifoaddr = M66592_D1FIFO;
  286. ep->fifosel = M66592_D1FIFOSEL;
  287. ep->fifoctr = M66592_D1FIFOCTR;
  288. ep->fifotrn = M66592_D1FIFOTRN;
  289. } else {
  290. ep->use_dma = 0;
  291. ep->fifoaddr = M66592_CFIFO;
  292. ep->fifosel = M66592_CFIFOSEL;
  293. ep->fifoctr = M66592_CFIFOCTR;
  294. ep->fifotrn = 0;
  295. }
  296. } else {
  297. ep->use_dma = 0;
  298. ep->fifoaddr = M66592_CFIFO;
  299. ep->fifosel = M66592_CFIFOSEL;
  300. ep->fifoctr = M66592_CFIFOCTR;
  301. ep->fifotrn = 0;
  302. }
  303. ep->pipectr = get_pipectr_addr(pipenum);
  304. ep->pipenum = pipenum;
  305. ep->ep.maxpacket = usb_endpoint_maxp(desc);
  306. m66592->pipenum2ep[pipenum] = ep;
  307. m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
  308. INIT_LIST_HEAD(&ep->queue);
  309. }
  310. static void m66592_ep_release(struct m66592_ep *ep)
  311. {
  312. struct m66592 *m66592 = ep->m66592;
  313. u16 pipenum = ep->pipenum;
  314. if (pipenum == 0)
  315. return;
  316. if (ep->use_dma)
  317. m66592->num_dma--;
  318. ep->pipenum = 0;
  319. ep->busy = 0;
  320. ep->use_dma = 0;
  321. }
  322. static int alloc_pipe_config(struct m66592_ep *ep,
  323. const struct usb_endpoint_descriptor *desc)
  324. {
  325. struct m66592 *m66592 = ep->m66592;
  326. struct m66592_pipe_info info;
  327. int dma = 0;
  328. int *counter;
  329. int ret;
  330. ep->ep.desc = desc;
  331. BUG_ON(ep->pipenum);
  332. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  333. case USB_ENDPOINT_XFER_BULK:
  334. if (m66592->bulk >= M66592_MAX_NUM_BULK) {
  335. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  336. pr_err("bulk pipe is insufficient\n");
  337. return -ENODEV;
  338. } else {
  339. info.pipe = M66592_BASE_PIPENUM_ISOC
  340. + m66592->isochronous;
  341. counter = &m66592->isochronous;
  342. }
  343. } else {
  344. info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
  345. counter = &m66592->bulk;
  346. }
  347. info.type = M66592_BULK;
  348. dma = 1;
  349. break;
  350. case USB_ENDPOINT_XFER_INT:
  351. if (m66592->interrupt >= M66592_MAX_NUM_INT) {
  352. pr_err("interrupt pipe is insufficient\n");
  353. return -ENODEV;
  354. }
  355. info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
  356. info.type = M66592_INT;
  357. counter = &m66592->interrupt;
  358. break;
  359. case USB_ENDPOINT_XFER_ISOC:
  360. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  361. pr_err("isochronous pipe is insufficient\n");
  362. return -ENODEV;
  363. }
  364. info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
  365. info.type = M66592_ISO;
  366. counter = &m66592->isochronous;
  367. break;
  368. default:
  369. pr_err("unexpect xfer type\n");
  370. return -EINVAL;
  371. }
  372. ep->type = info.type;
  373. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  374. info.maxpacket = usb_endpoint_maxp(desc);
  375. info.interval = desc->bInterval;
  376. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  377. info.dir_in = 1;
  378. else
  379. info.dir_in = 0;
  380. ret = pipe_buffer_setting(m66592, &info);
  381. if (ret < 0) {
  382. pr_err("pipe_buffer_setting fail\n");
  383. return ret;
  384. }
  385. (*counter)++;
  386. if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
  387. m66592->bulk++;
  388. m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
  389. pipe_initialize(ep);
  390. return 0;
  391. }
  392. static int free_pipe_config(struct m66592_ep *ep)
  393. {
  394. struct m66592 *m66592 = ep->m66592;
  395. struct m66592_pipe_info info;
  396. info.pipe = ep->pipenum;
  397. info.type = ep->type;
  398. pipe_buffer_release(m66592, &info);
  399. m66592_ep_release(ep);
  400. return 0;
  401. }
  402. /*-------------------------------------------------------------------------*/
  403. static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
  404. {
  405. enable_irq_ready(m66592, pipenum);
  406. enable_irq_nrdy(m66592, pipenum);
  407. }
  408. static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
  409. {
  410. disable_irq_ready(m66592, pipenum);
  411. disable_irq_nrdy(m66592, pipenum);
  412. }
  413. /* if complete is true, gadget driver complete function is not call */
  414. static void control_end(struct m66592 *m66592, unsigned ccpl)
  415. {
  416. m66592->ep[0].internal_ccpl = ccpl;
  417. pipe_start(m66592, 0);
  418. m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
  419. }
  420. static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  421. {
  422. struct m66592 *m66592 = ep->m66592;
  423. pipe_change(m66592, ep->pipenum);
  424. m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
  425. (M66592_ISEL | M66592_CURPIPE),
  426. M66592_CFIFOSEL);
  427. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  428. if (req->req.length == 0) {
  429. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  430. pipe_start(m66592, 0);
  431. transfer_complete(ep, req, 0);
  432. } else {
  433. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  434. irq_ep0_write(ep, req);
  435. }
  436. }
  437. static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  438. {
  439. struct m66592 *m66592 = ep->m66592;
  440. u16 tmp;
  441. pipe_change(m66592, ep->pipenum);
  442. disable_irq_empty(m66592, ep->pipenum);
  443. pipe_start(m66592, ep->pipenum);
  444. tmp = m66592_read(m66592, ep->fifoctr);
  445. if (unlikely((tmp & M66592_FRDY) == 0))
  446. pipe_irq_enable(m66592, ep->pipenum);
  447. else
  448. irq_packet_write(ep, req);
  449. }
  450. static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  451. {
  452. struct m66592 *m66592 = ep->m66592;
  453. u16 pipenum = ep->pipenum;
  454. if (ep->pipenum == 0) {
  455. m66592_mdfy(m66592, M66592_PIPE0,
  456. (M66592_ISEL | M66592_CURPIPE),
  457. M66592_CFIFOSEL);
  458. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  459. pipe_start(m66592, pipenum);
  460. pipe_irq_enable(m66592, pipenum);
  461. } else {
  462. if (ep->use_dma) {
  463. m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
  464. pipe_change(m66592, pipenum);
  465. m66592_bset(m66592, M66592_TRENB, ep->fifosel);
  466. m66592_write(m66592,
  467. (req->req.length + ep->ep.maxpacket - 1)
  468. / ep->ep.maxpacket,
  469. ep->fifotrn);
  470. }
  471. pipe_start(m66592, pipenum); /* trigger once */
  472. pipe_irq_enable(m66592, pipenum);
  473. }
  474. }
  475. static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
  476. {
  477. if (ep->ep.desc->bEndpointAddress & USB_DIR_IN)
  478. start_packet_write(ep, req);
  479. else
  480. start_packet_read(ep, req);
  481. }
  482. static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
  483. {
  484. u16 ctsq;
  485. ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
  486. switch (ctsq) {
  487. case M66592_CS_RDDS:
  488. start_ep0_write(ep, req);
  489. break;
  490. case M66592_CS_WRDS:
  491. start_packet_read(ep, req);
  492. break;
  493. case M66592_CS_WRND:
  494. control_end(ep->m66592, 0);
  495. break;
  496. default:
  497. pr_err("start_ep0: unexpect ctsq(%x)\n", ctsq);
  498. break;
  499. }
  500. }
  501. static void init_controller(struct m66592 *m66592)
  502. {
  503. unsigned int endian;
  504. if (m66592->pdata->on_chip) {
  505. if (m66592->pdata->endian)
  506. endian = 0; /* big endian */
  507. else
  508. endian = M66592_LITTLE; /* little endian */
  509. m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
  510. m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
  511. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  512. m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
  513. /* This is a workaound for SH7722 2nd cut */
  514. m66592_bset(m66592, 0x8000, M66592_DVSTCTR);
  515. m66592_bset(m66592, 0x1000, M66592_TESTMODE);
  516. m66592_bclr(m66592, 0x8000, M66592_DVSTCTR);
  517. m66592_bset(m66592, M66592_INTL, M66592_INTENB1);
  518. m66592_write(m66592, 0, M66592_CFBCFG);
  519. m66592_write(m66592, 0, M66592_D0FBCFG);
  520. m66592_bset(m66592, endian, M66592_CFBCFG);
  521. m66592_bset(m66592, endian, M66592_D0FBCFG);
  522. } else {
  523. unsigned int clock, vif, irq_sense;
  524. if (m66592->pdata->endian)
  525. endian = M66592_BIGEND; /* big endian */
  526. else
  527. endian = 0; /* little endian */
  528. if (m66592->pdata->vif)
  529. vif = M66592_LDRV; /* 3.3v */
  530. else
  531. vif = 0; /* 1.5v */
  532. switch (m66592->pdata->xtal) {
  533. case M66592_PLATDATA_XTAL_12MHZ:
  534. clock = M66592_XTAL12;
  535. break;
  536. case M66592_PLATDATA_XTAL_24MHZ:
  537. clock = M66592_XTAL24;
  538. break;
  539. case M66592_PLATDATA_XTAL_48MHZ:
  540. clock = M66592_XTAL48;
  541. break;
  542. default:
  543. pr_warning("m66592-udc: xtal configuration error\n");
  544. clock = 0;
  545. }
  546. switch (m66592->irq_trigger) {
  547. case IRQF_TRIGGER_LOW:
  548. irq_sense = M66592_INTL;
  549. break;
  550. case IRQF_TRIGGER_FALLING:
  551. irq_sense = 0;
  552. break;
  553. default:
  554. pr_warning("m66592-udc: irq trigger config error\n");
  555. irq_sense = 0;
  556. }
  557. m66592_bset(m66592,
  558. (vif & M66592_LDRV) | (endian & M66592_BIGEND),
  559. M66592_PINCFG);
  560. m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
  561. m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL,
  562. M66592_SYSCFG);
  563. m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
  564. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  565. m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
  566. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  567. msleep(3);
  568. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  569. msleep(1);
  570. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  571. m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
  572. m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
  573. M66592_DMA0CFG);
  574. }
  575. }
  576. static void disable_controller(struct m66592 *m66592)
  577. {
  578. m66592_bclr(m66592, M66592_UTST, M66592_TESTMODE);
  579. if (!m66592->pdata->on_chip) {
  580. m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
  581. udelay(1);
  582. m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
  583. udelay(1);
  584. m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
  585. udelay(1);
  586. m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
  587. }
  588. }
  589. static void m66592_start_xclock(struct m66592 *m66592)
  590. {
  591. u16 tmp;
  592. if (!m66592->pdata->on_chip) {
  593. tmp = m66592_read(m66592, M66592_SYSCFG);
  594. if (!(tmp & M66592_XCKE))
  595. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  596. }
  597. }
  598. /*-------------------------------------------------------------------------*/
  599. static void transfer_complete(struct m66592_ep *ep,
  600. struct m66592_request *req, int status)
  601. __releases(m66592->lock)
  602. __acquires(m66592->lock)
  603. {
  604. int restart = 0;
  605. if (unlikely(ep->pipenum == 0)) {
  606. if (ep->internal_ccpl) {
  607. ep->internal_ccpl = 0;
  608. return;
  609. }
  610. }
  611. list_del_init(&req->queue);
  612. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  613. req->req.status = -ESHUTDOWN;
  614. else
  615. req->req.status = status;
  616. if (!list_empty(&ep->queue))
  617. restart = 1;
  618. spin_unlock(&ep->m66592->lock);
  619. usb_gadget_giveback_request(&ep->ep, &req->req);
  620. spin_lock(&ep->m66592->lock);
  621. if (restart) {
  622. req = list_entry(ep->queue.next, struct m66592_request, queue);
  623. if (ep->ep.desc)
  624. start_packet(ep, req);
  625. }
  626. }
  627. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  628. {
  629. int i;
  630. u16 tmp;
  631. unsigned bufsize;
  632. size_t size;
  633. void *buf;
  634. u16 pipenum = ep->pipenum;
  635. struct m66592 *m66592 = ep->m66592;
  636. pipe_change(m66592, pipenum);
  637. m66592_bset(m66592, M66592_ISEL, ep->fifosel);
  638. i = 0;
  639. do {
  640. tmp = m66592_read(m66592, ep->fifoctr);
  641. if (i++ > 100000) {
  642. pr_err("pipe0 is busy. maybe cpu i/o bus "
  643. "conflict. please power off this controller.");
  644. return;
  645. }
  646. ndelay(1);
  647. } while ((tmp & M66592_FRDY) == 0);
  648. /* prepare parameters */
  649. bufsize = get_buffer_size(m66592, pipenum);
  650. buf = req->req.buf + req->req.actual;
  651. size = min(bufsize, req->req.length - req->req.actual);
  652. /* write fifo */
  653. if (req->req.buf) {
  654. if (size > 0)
  655. m66592_write_fifo(m66592, ep, buf, size);
  656. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  657. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  658. }
  659. /* update parameters */
  660. req->req.actual += size;
  661. /* check transfer finish */
  662. if ((!req->req.zero && (req->req.actual == req->req.length))
  663. || (size % ep->ep.maxpacket)
  664. || (size == 0)) {
  665. disable_irq_ready(m66592, pipenum);
  666. disable_irq_empty(m66592, pipenum);
  667. } else {
  668. disable_irq_ready(m66592, pipenum);
  669. enable_irq_empty(m66592, pipenum);
  670. }
  671. pipe_start(m66592, pipenum);
  672. }
  673. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  674. {
  675. u16 tmp;
  676. unsigned bufsize;
  677. size_t size;
  678. void *buf;
  679. u16 pipenum = ep->pipenum;
  680. struct m66592 *m66592 = ep->m66592;
  681. pipe_change(m66592, pipenum);
  682. tmp = m66592_read(m66592, ep->fifoctr);
  683. if (unlikely((tmp & M66592_FRDY) == 0)) {
  684. pipe_stop(m66592, pipenum);
  685. pipe_irq_disable(m66592, pipenum);
  686. pr_err("write fifo not ready. pipnum=%d\n", pipenum);
  687. return;
  688. }
  689. /* prepare parameters */
  690. bufsize = get_buffer_size(m66592, pipenum);
  691. buf = req->req.buf + req->req.actual;
  692. size = min(bufsize, req->req.length - req->req.actual);
  693. /* write fifo */
  694. if (req->req.buf) {
  695. m66592_write_fifo(m66592, ep, buf, size);
  696. if ((size == 0)
  697. || ((size % ep->ep.maxpacket) != 0)
  698. || ((bufsize != ep->ep.maxpacket)
  699. && (bufsize > size)))
  700. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  701. }
  702. /* update parameters */
  703. req->req.actual += size;
  704. /* check transfer finish */
  705. if ((!req->req.zero && (req->req.actual == req->req.length))
  706. || (size % ep->ep.maxpacket)
  707. || (size == 0)) {
  708. disable_irq_ready(m66592, pipenum);
  709. enable_irq_empty(m66592, pipenum);
  710. } else {
  711. disable_irq_empty(m66592, pipenum);
  712. pipe_irq_enable(m66592, pipenum);
  713. }
  714. }
  715. static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  716. {
  717. u16 tmp;
  718. int rcv_len, bufsize, req_len;
  719. int size;
  720. void *buf;
  721. u16 pipenum = ep->pipenum;
  722. struct m66592 *m66592 = ep->m66592;
  723. int finish = 0;
  724. pipe_change(m66592, pipenum);
  725. tmp = m66592_read(m66592, ep->fifoctr);
  726. if (unlikely((tmp & M66592_FRDY) == 0)) {
  727. req->req.status = -EPIPE;
  728. pipe_stop(m66592, pipenum);
  729. pipe_irq_disable(m66592, pipenum);
  730. pr_err("read fifo not ready");
  731. return;
  732. }
  733. /* prepare parameters */
  734. rcv_len = tmp & M66592_DTLN;
  735. bufsize = get_buffer_size(m66592, pipenum);
  736. buf = req->req.buf + req->req.actual;
  737. req_len = req->req.length - req->req.actual;
  738. if (rcv_len < bufsize)
  739. size = min(rcv_len, req_len);
  740. else
  741. size = min(bufsize, req_len);
  742. /* update parameters */
  743. req->req.actual += size;
  744. /* check transfer finish */
  745. if ((!req->req.zero && (req->req.actual == req->req.length))
  746. || (size % ep->ep.maxpacket)
  747. || (size == 0)) {
  748. pipe_stop(m66592, pipenum);
  749. pipe_irq_disable(m66592, pipenum);
  750. finish = 1;
  751. }
  752. /* read fifo */
  753. if (req->req.buf) {
  754. if (size == 0)
  755. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  756. else
  757. m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
  758. }
  759. if ((ep->pipenum != 0) && finish)
  760. transfer_complete(ep, req, 0);
  761. }
  762. static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
  763. {
  764. u16 check;
  765. u16 pipenum;
  766. struct m66592_ep *ep;
  767. struct m66592_request *req;
  768. if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
  769. m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
  770. m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
  771. M66592_CFIFOSEL);
  772. ep = &m66592->ep[0];
  773. req = list_entry(ep->queue.next, struct m66592_request, queue);
  774. irq_packet_read(ep, req);
  775. } else {
  776. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  777. check = 1 << pipenum;
  778. if ((status & check) && (enb & check)) {
  779. m66592_write(m66592, ~check, M66592_BRDYSTS);
  780. ep = m66592->pipenum2ep[pipenum];
  781. req = list_entry(ep->queue.next,
  782. struct m66592_request, queue);
  783. if (ep->ep.desc->bEndpointAddress & USB_DIR_IN)
  784. irq_packet_write(ep, req);
  785. else
  786. irq_packet_read(ep, req);
  787. }
  788. }
  789. }
  790. }
  791. static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
  792. {
  793. u16 tmp;
  794. u16 check;
  795. u16 pipenum;
  796. struct m66592_ep *ep;
  797. struct m66592_request *req;
  798. if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
  799. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  800. ep = &m66592->ep[0];
  801. req = list_entry(ep->queue.next, struct m66592_request, queue);
  802. irq_ep0_write(ep, req);
  803. } else {
  804. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  805. check = 1 << pipenum;
  806. if ((status & check) && (enb & check)) {
  807. m66592_write(m66592, ~check, M66592_BEMPSTS);
  808. tmp = control_reg_get(m66592, pipenum);
  809. if ((tmp & M66592_INBUFM) == 0) {
  810. disable_irq_empty(m66592, pipenum);
  811. pipe_irq_disable(m66592, pipenum);
  812. pipe_stop(m66592, pipenum);
  813. ep = m66592->pipenum2ep[pipenum];
  814. req = list_entry(ep->queue.next,
  815. struct m66592_request,
  816. queue);
  817. if (!list_empty(&ep->queue))
  818. transfer_complete(ep, req, 0);
  819. }
  820. }
  821. }
  822. }
  823. }
  824. static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  825. __releases(m66592->lock)
  826. __acquires(m66592->lock)
  827. {
  828. struct m66592_ep *ep;
  829. u16 pid;
  830. u16 status = 0;
  831. u16 w_index = le16_to_cpu(ctrl->wIndex);
  832. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  833. case USB_RECIP_DEVICE:
  834. status = 1 << USB_DEVICE_SELF_POWERED;
  835. break;
  836. case USB_RECIP_INTERFACE:
  837. status = 0;
  838. break;
  839. case USB_RECIP_ENDPOINT:
  840. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  841. pid = control_reg_get_pid(m66592, ep->pipenum);
  842. if (pid == M66592_PID_STALL)
  843. status = 1 << USB_ENDPOINT_HALT;
  844. else
  845. status = 0;
  846. break;
  847. default:
  848. pipe_stall(m66592, 0);
  849. return; /* exit */
  850. }
  851. m66592->ep0_data = cpu_to_le16(status);
  852. m66592->ep0_req->buf = &m66592->ep0_data;
  853. m66592->ep0_req->length = 2;
  854. /* AV: what happens if we get called again before that gets through? */
  855. spin_unlock(&m66592->lock);
  856. m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
  857. spin_lock(&m66592->lock);
  858. }
  859. static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  860. {
  861. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  862. case USB_RECIP_DEVICE:
  863. control_end(m66592, 1);
  864. break;
  865. case USB_RECIP_INTERFACE:
  866. control_end(m66592, 1);
  867. break;
  868. case USB_RECIP_ENDPOINT: {
  869. struct m66592_ep *ep;
  870. struct m66592_request *req;
  871. u16 w_index = le16_to_cpu(ctrl->wIndex);
  872. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  873. pipe_stop(m66592, ep->pipenum);
  874. control_reg_sqclr(m66592, ep->pipenum);
  875. control_end(m66592, 1);
  876. req = list_entry(ep->queue.next,
  877. struct m66592_request, queue);
  878. if (ep->busy) {
  879. ep->busy = 0;
  880. if (list_empty(&ep->queue))
  881. break;
  882. start_packet(ep, req);
  883. } else if (!list_empty(&ep->queue))
  884. pipe_start(m66592, ep->pipenum);
  885. }
  886. break;
  887. default:
  888. pipe_stall(m66592, 0);
  889. break;
  890. }
  891. }
  892. static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  893. {
  894. u16 tmp;
  895. int timeout = 3000;
  896. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  897. case USB_RECIP_DEVICE:
  898. switch (le16_to_cpu(ctrl->wValue)) {
  899. case USB_DEVICE_TEST_MODE:
  900. control_end(m66592, 1);
  901. /* Wait for the completion of status stage */
  902. do {
  903. tmp = m66592_read(m66592, M66592_INTSTS0) &
  904. M66592_CTSQ;
  905. udelay(1);
  906. } while (tmp != M66592_CS_IDST && timeout-- > 0);
  907. if (tmp == M66592_CS_IDST)
  908. m66592_bset(m66592,
  909. le16_to_cpu(ctrl->wIndex >> 8),
  910. M66592_TESTMODE);
  911. break;
  912. default:
  913. pipe_stall(m66592, 0);
  914. break;
  915. }
  916. break;
  917. case USB_RECIP_INTERFACE:
  918. control_end(m66592, 1);
  919. break;
  920. case USB_RECIP_ENDPOINT: {
  921. struct m66592_ep *ep;
  922. u16 w_index = le16_to_cpu(ctrl->wIndex);
  923. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  924. pipe_stall(m66592, ep->pipenum);
  925. control_end(m66592, 1);
  926. }
  927. break;
  928. default:
  929. pipe_stall(m66592, 0);
  930. break;
  931. }
  932. }
  933. /* if return value is true, call class driver's setup() */
  934. static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  935. {
  936. u16 *p = (u16 *)ctrl;
  937. unsigned long offset = M66592_USBREQ;
  938. int i, ret = 0;
  939. /* read fifo */
  940. m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
  941. for (i = 0; i < 4; i++)
  942. p[i] = m66592_read(m66592, offset + i*2);
  943. /* check request */
  944. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  945. switch (ctrl->bRequest) {
  946. case USB_REQ_GET_STATUS:
  947. get_status(m66592, ctrl);
  948. break;
  949. case USB_REQ_CLEAR_FEATURE:
  950. clear_feature(m66592, ctrl);
  951. break;
  952. case USB_REQ_SET_FEATURE:
  953. set_feature(m66592, ctrl);
  954. break;
  955. default:
  956. ret = 1;
  957. break;
  958. }
  959. } else
  960. ret = 1;
  961. return ret;
  962. }
  963. static void m66592_update_usb_speed(struct m66592 *m66592)
  964. {
  965. u16 speed = get_usb_speed(m66592);
  966. switch (speed) {
  967. case M66592_HSMODE:
  968. m66592->gadget.speed = USB_SPEED_HIGH;
  969. break;
  970. case M66592_FSMODE:
  971. m66592->gadget.speed = USB_SPEED_FULL;
  972. break;
  973. default:
  974. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  975. pr_err("USB speed unknown\n");
  976. }
  977. }
  978. static void irq_device_state(struct m66592 *m66592)
  979. {
  980. u16 dvsq;
  981. dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
  982. m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
  983. if (dvsq == M66592_DS_DFLT) { /* bus reset */
  984. usb_gadget_udc_reset(&m66592->gadget, m66592->driver);
  985. m66592_update_usb_speed(m66592);
  986. }
  987. if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
  988. m66592_update_usb_speed(m66592);
  989. if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
  990. && m66592->gadget.speed == USB_SPEED_UNKNOWN)
  991. m66592_update_usb_speed(m66592);
  992. m66592->old_dvsq = dvsq;
  993. }
  994. static void irq_control_stage(struct m66592 *m66592)
  995. __releases(m66592->lock)
  996. __acquires(m66592->lock)
  997. {
  998. struct usb_ctrlrequest ctrl;
  999. u16 ctsq;
  1000. ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
  1001. m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
  1002. switch (ctsq) {
  1003. case M66592_CS_IDST: {
  1004. struct m66592_ep *ep;
  1005. struct m66592_request *req;
  1006. ep = &m66592->ep[0];
  1007. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1008. transfer_complete(ep, req, 0);
  1009. }
  1010. break;
  1011. case M66592_CS_RDDS:
  1012. case M66592_CS_WRDS:
  1013. case M66592_CS_WRND:
  1014. if (setup_packet(m66592, &ctrl)) {
  1015. spin_unlock(&m66592->lock);
  1016. if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
  1017. pipe_stall(m66592, 0);
  1018. spin_lock(&m66592->lock);
  1019. }
  1020. break;
  1021. case M66592_CS_RDSS:
  1022. case M66592_CS_WRSS:
  1023. control_end(m66592, 0);
  1024. break;
  1025. default:
  1026. pr_err("ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  1027. break;
  1028. }
  1029. }
  1030. static irqreturn_t m66592_irq(int irq, void *_m66592)
  1031. {
  1032. struct m66592 *m66592 = _m66592;
  1033. u16 intsts0;
  1034. u16 intenb0;
  1035. u16 brdysts, nrdysts, bempsts;
  1036. u16 brdyenb, nrdyenb, bempenb;
  1037. u16 savepipe;
  1038. u16 mask0;
  1039. spin_lock(&m66592->lock);
  1040. intsts0 = m66592_read(m66592, M66592_INTSTS0);
  1041. intenb0 = m66592_read(m66592, M66592_INTENB0);
  1042. if (m66592->pdata->on_chip && !intsts0 && !intenb0) {
  1043. /*
  1044. * When USB clock stops, it cannot read register. Even if a
  1045. * clock stops, the interrupt occurs. So this driver turn on
  1046. * a clock by this timing and do re-reading of register.
  1047. */
  1048. m66592_start_xclock(m66592);
  1049. intsts0 = m66592_read(m66592, M66592_INTSTS0);
  1050. intenb0 = m66592_read(m66592, M66592_INTENB0);
  1051. }
  1052. savepipe = m66592_read(m66592, M66592_CFIFOSEL);
  1053. mask0 = intsts0 & intenb0;
  1054. if (mask0) {
  1055. brdysts = m66592_read(m66592, M66592_BRDYSTS);
  1056. nrdysts = m66592_read(m66592, M66592_NRDYSTS);
  1057. bempsts = m66592_read(m66592, M66592_BEMPSTS);
  1058. brdyenb = m66592_read(m66592, M66592_BRDYENB);
  1059. nrdyenb = m66592_read(m66592, M66592_NRDYENB);
  1060. bempenb = m66592_read(m66592, M66592_BEMPENB);
  1061. if (mask0 & M66592_VBINT) {
  1062. m66592_write(m66592, 0xffff & ~M66592_VBINT,
  1063. M66592_INTSTS0);
  1064. m66592_start_xclock(m66592);
  1065. /* start vbus sampling */
  1066. m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
  1067. & M66592_VBSTS;
  1068. m66592->scount = M66592_MAX_SAMPLING;
  1069. mod_timer(&m66592->timer,
  1070. jiffies + msecs_to_jiffies(50));
  1071. }
  1072. if (intsts0 & M66592_DVSQ)
  1073. irq_device_state(m66592);
  1074. if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
  1075. && (brdysts & brdyenb)) {
  1076. irq_pipe_ready(m66592, brdysts, brdyenb);
  1077. }
  1078. if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
  1079. && (bempsts & bempenb)) {
  1080. irq_pipe_empty(m66592, bempsts, bempenb);
  1081. }
  1082. if (intsts0 & M66592_CTRT)
  1083. irq_control_stage(m66592);
  1084. }
  1085. m66592_write(m66592, savepipe, M66592_CFIFOSEL);
  1086. spin_unlock(&m66592->lock);
  1087. return IRQ_HANDLED;
  1088. }
  1089. static void m66592_timer(unsigned long _m66592)
  1090. {
  1091. struct m66592 *m66592 = (struct m66592 *)_m66592;
  1092. unsigned long flags;
  1093. u16 tmp;
  1094. spin_lock_irqsave(&m66592->lock, flags);
  1095. tmp = m66592_read(m66592, M66592_SYSCFG);
  1096. if (!(tmp & M66592_RCKE)) {
  1097. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  1098. udelay(10);
  1099. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  1100. }
  1101. if (m66592->scount > 0) {
  1102. tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
  1103. if (tmp == m66592->old_vbus) {
  1104. m66592->scount--;
  1105. if (m66592->scount == 0) {
  1106. if (tmp == M66592_VBSTS)
  1107. m66592_usb_connect(m66592);
  1108. else
  1109. m66592_usb_disconnect(m66592);
  1110. } else {
  1111. mod_timer(&m66592->timer,
  1112. jiffies + msecs_to_jiffies(50));
  1113. }
  1114. } else {
  1115. m66592->scount = M66592_MAX_SAMPLING;
  1116. m66592->old_vbus = tmp;
  1117. mod_timer(&m66592->timer,
  1118. jiffies + msecs_to_jiffies(50));
  1119. }
  1120. }
  1121. spin_unlock_irqrestore(&m66592->lock, flags);
  1122. }
  1123. /*-------------------------------------------------------------------------*/
  1124. static int m66592_enable(struct usb_ep *_ep,
  1125. const struct usb_endpoint_descriptor *desc)
  1126. {
  1127. struct m66592_ep *ep;
  1128. ep = container_of(_ep, struct m66592_ep, ep);
  1129. return alloc_pipe_config(ep, desc);
  1130. }
  1131. static int m66592_disable(struct usb_ep *_ep)
  1132. {
  1133. struct m66592_ep *ep;
  1134. struct m66592_request *req;
  1135. unsigned long flags;
  1136. ep = container_of(_ep, struct m66592_ep, ep);
  1137. BUG_ON(!ep);
  1138. while (!list_empty(&ep->queue)) {
  1139. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1140. spin_lock_irqsave(&ep->m66592->lock, flags);
  1141. transfer_complete(ep, req, -ECONNRESET);
  1142. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1143. }
  1144. pipe_irq_disable(ep->m66592, ep->pipenum);
  1145. return free_pipe_config(ep);
  1146. }
  1147. static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
  1148. gfp_t gfp_flags)
  1149. {
  1150. struct m66592_request *req;
  1151. req = kzalloc(sizeof(struct m66592_request), gfp_flags);
  1152. if (!req)
  1153. return NULL;
  1154. INIT_LIST_HEAD(&req->queue);
  1155. return &req->req;
  1156. }
  1157. static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1158. {
  1159. struct m66592_request *req;
  1160. req = container_of(_req, struct m66592_request, req);
  1161. kfree(req);
  1162. }
  1163. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  1164. gfp_t gfp_flags)
  1165. {
  1166. struct m66592_ep *ep;
  1167. struct m66592_request *req;
  1168. unsigned long flags;
  1169. int request = 0;
  1170. ep = container_of(_ep, struct m66592_ep, ep);
  1171. req = container_of(_req, struct m66592_request, req);
  1172. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  1173. return -ESHUTDOWN;
  1174. spin_lock_irqsave(&ep->m66592->lock, flags);
  1175. if (list_empty(&ep->queue))
  1176. request = 1;
  1177. list_add_tail(&req->queue, &ep->queue);
  1178. req->req.actual = 0;
  1179. req->req.status = -EINPROGRESS;
  1180. if (ep->ep.desc == NULL) /* control */
  1181. start_ep0(ep, req);
  1182. else {
  1183. if (request && !ep->busy)
  1184. start_packet(ep, req);
  1185. }
  1186. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1187. return 0;
  1188. }
  1189. static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1190. {
  1191. struct m66592_ep *ep;
  1192. struct m66592_request *req;
  1193. unsigned long flags;
  1194. ep = container_of(_ep, struct m66592_ep, ep);
  1195. req = container_of(_req, struct m66592_request, req);
  1196. spin_lock_irqsave(&ep->m66592->lock, flags);
  1197. if (!list_empty(&ep->queue))
  1198. transfer_complete(ep, req, -ECONNRESET);
  1199. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1200. return 0;
  1201. }
  1202. static int m66592_set_halt(struct usb_ep *_ep, int value)
  1203. {
  1204. struct m66592_ep *ep;
  1205. struct m66592_request *req;
  1206. unsigned long flags;
  1207. int ret = 0;
  1208. ep = container_of(_ep, struct m66592_ep, ep);
  1209. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1210. spin_lock_irqsave(&ep->m66592->lock, flags);
  1211. if (!list_empty(&ep->queue)) {
  1212. ret = -EAGAIN;
  1213. goto out;
  1214. }
  1215. if (value) {
  1216. ep->busy = 1;
  1217. pipe_stall(ep->m66592, ep->pipenum);
  1218. } else {
  1219. ep->busy = 0;
  1220. pipe_stop(ep->m66592, ep->pipenum);
  1221. }
  1222. out:
  1223. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1224. return ret;
  1225. }
  1226. static void m66592_fifo_flush(struct usb_ep *_ep)
  1227. {
  1228. struct m66592_ep *ep;
  1229. unsigned long flags;
  1230. ep = container_of(_ep, struct m66592_ep, ep);
  1231. spin_lock_irqsave(&ep->m66592->lock, flags);
  1232. if (list_empty(&ep->queue) && !ep->busy) {
  1233. pipe_stop(ep->m66592, ep->pipenum);
  1234. m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
  1235. }
  1236. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1237. }
  1238. static struct usb_ep_ops m66592_ep_ops = {
  1239. .enable = m66592_enable,
  1240. .disable = m66592_disable,
  1241. .alloc_request = m66592_alloc_request,
  1242. .free_request = m66592_free_request,
  1243. .queue = m66592_queue,
  1244. .dequeue = m66592_dequeue,
  1245. .set_halt = m66592_set_halt,
  1246. .fifo_flush = m66592_fifo_flush,
  1247. };
  1248. /*-------------------------------------------------------------------------*/
  1249. static int m66592_udc_start(struct usb_gadget *g,
  1250. struct usb_gadget_driver *driver)
  1251. {
  1252. struct m66592 *m66592 = to_m66592(g);
  1253. /* hook up the driver */
  1254. driver->driver.bus = NULL;
  1255. m66592->driver = driver;
  1256. m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1257. if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
  1258. m66592_start_xclock(m66592);
  1259. /* start vbus sampling */
  1260. m66592->old_vbus = m66592_read(m66592,
  1261. M66592_INTSTS0) & M66592_VBSTS;
  1262. m66592->scount = M66592_MAX_SAMPLING;
  1263. mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
  1264. }
  1265. return 0;
  1266. }
  1267. static int m66592_udc_stop(struct usb_gadget *g)
  1268. {
  1269. struct m66592 *m66592 = to_m66592(g);
  1270. m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1271. init_controller(m66592);
  1272. disable_controller(m66592);
  1273. m66592->driver = NULL;
  1274. return 0;
  1275. }
  1276. /*-------------------------------------------------------------------------*/
  1277. static int m66592_get_frame(struct usb_gadget *_gadget)
  1278. {
  1279. struct m66592 *m66592 = gadget_to_m66592(_gadget);
  1280. return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
  1281. }
  1282. static int m66592_pullup(struct usb_gadget *gadget, int is_on)
  1283. {
  1284. struct m66592 *m66592 = gadget_to_m66592(gadget);
  1285. unsigned long flags;
  1286. spin_lock_irqsave(&m66592->lock, flags);
  1287. if (is_on)
  1288. m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
  1289. else
  1290. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  1291. spin_unlock_irqrestore(&m66592->lock, flags);
  1292. return 0;
  1293. }
  1294. static const struct usb_gadget_ops m66592_gadget_ops = {
  1295. .get_frame = m66592_get_frame,
  1296. .udc_start = m66592_udc_start,
  1297. .udc_stop = m66592_udc_stop,
  1298. .pullup = m66592_pullup,
  1299. };
  1300. static int m66592_remove(struct platform_device *pdev)
  1301. {
  1302. struct m66592 *m66592 = platform_get_drvdata(pdev);
  1303. usb_del_gadget_udc(&m66592->gadget);
  1304. del_timer_sync(&m66592->timer);
  1305. iounmap(m66592->reg);
  1306. free_irq(platform_get_irq(pdev, 0), m66592);
  1307. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1308. if (m66592->pdata->on_chip) {
  1309. clk_disable(m66592->clk);
  1310. clk_put(m66592->clk);
  1311. }
  1312. kfree(m66592);
  1313. return 0;
  1314. }
  1315. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1316. {
  1317. }
  1318. static int m66592_probe(struct platform_device *pdev)
  1319. {
  1320. struct resource *res, *ires;
  1321. void __iomem *reg = NULL;
  1322. struct m66592 *m66592 = NULL;
  1323. char clk_name[8];
  1324. int ret = 0;
  1325. int i;
  1326. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1327. if (!res) {
  1328. ret = -ENODEV;
  1329. pr_err("platform_get_resource error.\n");
  1330. goto clean_up;
  1331. }
  1332. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1333. if (!ires) {
  1334. ret = -ENODEV;
  1335. dev_err(&pdev->dev,
  1336. "platform_get_resource IORESOURCE_IRQ error.\n");
  1337. goto clean_up;
  1338. }
  1339. reg = ioremap(res->start, resource_size(res));
  1340. if (reg == NULL) {
  1341. ret = -ENOMEM;
  1342. pr_err("ioremap error.\n");
  1343. goto clean_up;
  1344. }
  1345. if (dev_get_platdata(&pdev->dev) == NULL) {
  1346. dev_err(&pdev->dev, "no platform data\n");
  1347. ret = -ENODEV;
  1348. goto clean_up;
  1349. }
  1350. /* initialize ucd */
  1351. m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
  1352. if (m66592 == NULL) {
  1353. ret = -ENOMEM;
  1354. goto clean_up;
  1355. }
  1356. m66592->pdata = dev_get_platdata(&pdev->dev);
  1357. m66592->irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
  1358. spin_lock_init(&m66592->lock);
  1359. platform_set_drvdata(pdev, m66592);
  1360. m66592->gadget.ops = &m66592_gadget_ops;
  1361. m66592->gadget.max_speed = USB_SPEED_HIGH;
  1362. m66592->gadget.name = udc_name;
  1363. init_timer(&m66592->timer);
  1364. m66592->timer.function = m66592_timer;
  1365. m66592->timer.data = (unsigned long)m66592;
  1366. m66592->reg = reg;
  1367. ret = request_irq(ires->start, m66592_irq, IRQF_SHARED,
  1368. udc_name, m66592);
  1369. if (ret < 0) {
  1370. pr_err("request_irq error (%d)\n", ret);
  1371. goto clean_up;
  1372. }
  1373. if (m66592->pdata->on_chip) {
  1374. snprintf(clk_name, sizeof(clk_name), "usbf%d", pdev->id);
  1375. m66592->clk = clk_get(&pdev->dev, clk_name);
  1376. if (IS_ERR(m66592->clk)) {
  1377. dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
  1378. clk_name);
  1379. ret = PTR_ERR(m66592->clk);
  1380. goto clean_up2;
  1381. }
  1382. clk_enable(m66592->clk);
  1383. }
  1384. INIT_LIST_HEAD(&m66592->gadget.ep_list);
  1385. m66592->gadget.ep0 = &m66592->ep[0].ep;
  1386. INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
  1387. for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
  1388. struct m66592_ep *ep = &m66592->ep[i];
  1389. if (i != 0) {
  1390. INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
  1391. list_add_tail(&m66592->ep[i].ep.ep_list,
  1392. &m66592->gadget.ep_list);
  1393. }
  1394. ep->m66592 = m66592;
  1395. INIT_LIST_HEAD(&ep->queue);
  1396. ep->ep.name = m66592_ep_name[i];
  1397. ep->ep.ops = &m66592_ep_ops;
  1398. usb_ep_set_maxpacket_limit(&ep->ep, 512);
  1399. if (i == 0) {
  1400. ep->ep.caps.type_control = true;
  1401. } else {
  1402. ep->ep.caps.type_iso = true;
  1403. ep->ep.caps.type_bulk = true;
  1404. ep->ep.caps.type_int = true;
  1405. }
  1406. ep->ep.caps.dir_in = true;
  1407. ep->ep.caps.dir_out = true;
  1408. }
  1409. usb_ep_set_maxpacket_limit(&m66592->ep[0].ep, 64);
  1410. m66592->ep[0].pipenum = 0;
  1411. m66592->ep[0].fifoaddr = M66592_CFIFO;
  1412. m66592->ep[0].fifosel = M66592_CFIFOSEL;
  1413. m66592->ep[0].fifoctr = M66592_CFIFOCTR;
  1414. m66592->ep[0].fifotrn = 0;
  1415. m66592->ep[0].pipectr = get_pipectr_addr(0);
  1416. m66592->pipenum2ep[0] = &m66592->ep[0];
  1417. m66592->epaddr2ep[0] = &m66592->ep[0];
  1418. m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
  1419. if (m66592->ep0_req == NULL) {
  1420. ret = -ENOMEM;
  1421. goto clean_up3;
  1422. }
  1423. m66592->ep0_req->complete = nop_completion;
  1424. init_controller(m66592);
  1425. ret = usb_add_gadget_udc(&pdev->dev, &m66592->gadget);
  1426. if (ret)
  1427. goto err_add_udc;
  1428. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1429. return 0;
  1430. err_add_udc:
  1431. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1432. clean_up3:
  1433. if (m66592->pdata->on_chip) {
  1434. clk_disable(m66592->clk);
  1435. clk_put(m66592->clk);
  1436. }
  1437. clean_up2:
  1438. free_irq(ires->start, m66592);
  1439. clean_up:
  1440. if (m66592) {
  1441. if (m66592->ep0_req)
  1442. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1443. kfree(m66592);
  1444. }
  1445. if (reg)
  1446. iounmap(reg);
  1447. return ret;
  1448. }
  1449. /*-------------------------------------------------------------------------*/
  1450. static struct platform_driver m66592_driver = {
  1451. .remove = m66592_remove,
  1452. .driver = {
  1453. .name = (char *) udc_name,
  1454. },
  1455. };
  1456. module_platform_driver_probe(m66592_driver, m66592_probe);