pxa25x_udc.h 6.4 KB

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  1. /*
  2. * Intel PXA25x on-chip full speed USB device controller
  3. *
  4. * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
  5. * Copyright (C) 2003 David Brownell
  6. *
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #ifndef __LINUX_USB_GADGET_PXA25X_H
  14. #define __LINUX_USB_GADGET_PXA25X_H
  15. #include <linux/types.h>
  16. /*-------------------------------------------------------------------------*/
  17. /* pxa25x has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */
  18. #define UFNRH_SIR (1 << 7) /* SOF interrupt request */
  19. #define UFNRH_SIM (1 << 6) /* SOF interrupt mask */
  20. #define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */
  21. #define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */
  22. #define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */
  23. /* pxa255 has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */
  24. #define UDCCFR UDC_RES2 /* UDC Control Function Register */
  25. #define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */
  26. #define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */
  27. /* latest pxa255 errata define new "must be one" bits in UDCCFR */
  28. #define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN|UDCCFR_ACM))
  29. /*-------------------------------------------------------------------------*/
  30. struct pxa25x_udc;
  31. struct pxa25x_ep {
  32. struct usb_ep ep;
  33. struct pxa25x_udc *dev;
  34. struct list_head queue;
  35. unsigned long pio_irqs;
  36. unsigned short fifo_size;
  37. u8 bEndpointAddress;
  38. u8 bmAttributes;
  39. unsigned stopped : 1;
  40. unsigned dma_fixup : 1;
  41. /* UDCCS = UDC Control/Status for this EP
  42. * UBCR = UDC Byte Count Remaining (contents of OUT fifo)
  43. * UDDR = UDC Endpoint Data Register (the fifo)
  44. * DRCM = DMA Request Channel Map
  45. */
  46. volatile u32 *reg_udccs;
  47. volatile u32 *reg_ubcr;
  48. volatile u32 *reg_uddr;
  49. };
  50. struct pxa25x_request {
  51. struct usb_request req;
  52. struct list_head queue;
  53. };
  54. enum ep0_state {
  55. EP0_IDLE,
  56. EP0_IN_DATA_PHASE,
  57. EP0_OUT_DATA_PHASE,
  58. EP0_END_XFER,
  59. EP0_STALL,
  60. };
  61. #define EP0_FIFO_SIZE ((unsigned)16)
  62. #define BULK_FIFO_SIZE ((unsigned)64)
  63. #define ISO_FIFO_SIZE ((unsigned)256)
  64. #define INT_FIFO_SIZE ((unsigned)8)
  65. struct udc_stats {
  66. struct ep0stats {
  67. unsigned long ops;
  68. unsigned long bytes;
  69. } read, write;
  70. unsigned long irqs;
  71. };
  72. #ifdef CONFIG_USB_PXA25X_SMALL
  73. /* when memory's tight, SMALL config saves code+data. */
  74. #define PXA_UDC_NUM_ENDPOINTS 3
  75. #endif
  76. #ifndef PXA_UDC_NUM_ENDPOINTS
  77. #define PXA_UDC_NUM_ENDPOINTS 16
  78. #endif
  79. struct pxa25x_udc {
  80. struct usb_gadget gadget;
  81. struct usb_gadget_driver *driver;
  82. enum ep0_state ep0state;
  83. struct udc_stats stats;
  84. unsigned got_irq : 1,
  85. vbus : 1,
  86. pullup : 1,
  87. has_cfr : 1,
  88. req_pending : 1,
  89. req_std : 1,
  90. req_config : 1,
  91. suspended : 1,
  92. active : 1;
  93. #define start_watchdog(dev) mod_timer(&dev->timer, jiffies + (HZ/200))
  94. struct timer_list timer;
  95. struct device *dev;
  96. struct clk *clk;
  97. struct pxa2xx_udc_mach_info *mach;
  98. struct usb_phy *transceiver;
  99. u64 dma_mask;
  100. struct pxa25x_ep ep [PXA_UDC_NUM_ENDPOINTS];
  101. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  102. struct dentry *debugfs_udc;
  103. #endif
  104. };
  105. #define to_pxa25x(g) (container_of((g), struct pxa25x_udc, gadget))
  106. /*-------------------------------------------------------------------------*/
  107. #ifdef CONFIG_ARCH_LUBBOCK
  108. #include <mach/lubbock.h>
  109. /* lubbock can also report usb connect/disconnect irqs */
  110. #endif
  111. static struct pxa25x_udc *the_controller;
  112. /*-------------------------------------------------------------------------*/
  113. /*
  114. * Debugging support vanishes in non-debug builds. DBG_NORMAL should be
  115. * mostly silent during normal use/testing, with no timing side-effects.
  116. */
  117. #define DBG_NORMAL 1 /* error paths, device state transitions */
  118. #define DBG_VERBOSE 2 /* add some success path trace info */
  119. #define DBG_NOISY 3 /* ... even more: request level */
  120. #define DBG_VERY_NOISY 4 /* ... even more: packet level */
  121. #define DMSG(stuff...) pr_debug("udc: " stuff)
  122. #ifdef DEBUG
  123. static const char *state_name[] = {
  124. "EP0_IDLE",
  125. "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
  126. "EP0_END_XFER", "EP0_STALL"
  127. };
  128. #ifdef VERBOSE_DEBUG
  129. # define UDC_DEBUG DBG_VERBOSE
  130. #else
  131. # define UDC_DEBUG DBG_NORMAL
  132. #endif
  133. static void __maybe_unused
  134. dump_udccr(const char *label)
  135. {
  136. u32 udccr = UDCCR;
  137. DMSG("%s %02X =%s%s%s%s%s%s%s%s\n",
  138. label, udccr,
  139. (udccr & UDCCR_REM) ? " rem" : "",
  140. (udccr & UDCCR_RSTIR) ? " rstir" : "",
  141. (udccr & UDCCR_SRM) ? " srm" : "",
  142. (udccr & UDCCR_SUSIR) ? " susir" : "",
  143. (udccr & UDCCR_RESIR) ? " resir" : "",
  144. (udccr & UDCCR_RSM) ? " rsm" : "",
  145. (udccr & UDCCR_UDA) ? " uda" : "",
  146. (udccr & UDCCR_UDE) ? " ude" : "");
  147. }
  148. static void __maybe_unused
  149. dump_udccs0(const char *label)
  150. {
  151. u32 udccs0 = UDCCS0;
  152. DMSG("%s %s %02X =%s%s%s%s%s%s%s%s\n",
  153. label, state_name[the_controller->ep0state], udccs0,
  154. (udccs0 & UDCCS0_SA) ? " sa" : "",
  155. (udccs0 & UDCCS0_RNE) ? " rne" : "",
  156. (udccs0 & UDCCS0_FST) ? " fst" : "",
  157. (udccs0 & UDCCS0_SST) ? " sst" : "",
  158. (udccs0 & UDCCS0_DRWF) ? " dwrf" : "",
  159. (udccs0 & UDCCS0_FTF) ? " ftf" : "",
  160. (udccs0 & UDCCS0_IPR) ? " ipr" : "",
  161. (udccs0 & UDCCS0_OPR) ? " opr" : "");
  162. }
  163. static void __maybe_unused
  164. dump_state(struct pxa25x_udc *dev)
  165. {
  166. u32 tmp;
  167. unsigned i;
  168. DMSG("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
  169. state_name[dev->ep0state],
  170. UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL);
  171. dump_udccr("udccr");
  172. if (dev->has_cfr) {
  173. tmp = UDCCFR;
  174. DMSG("udccfr %02X =%s%s\n", tmp,
  175. (tmp & UDCCFR_AREN) ? " aren" : "",
  176. (tmp & UDCCFR_ACM) ? " acm" : "");
  177. }
  178. if (!dev->driver) {
  179. DMSG("no gadget driver bound\n");
  180. return;
  181. } else
  182. DMSG("ep0 driver '%s'\n", dev->driver->driver.name);
  183. dump_udccs0 ("udccs0");
  184. DMSG("ep0 IN %lu/%lu, OUT %lu/%lu\n",
  185. dev->stats.write.bytes, dev->stats.write.ops,
  186. dev->stats.read.bytes, dev->stats.read.ops);
  187. for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) {
  188. if (dev->ep[i].ep.desc == NULL)
  189. continue;
  190. DMSG ("udccs%d = %02x\n", i, *dev->ep->reg_udccs);
  191. }
  192. }
  193. #else
  194. #define dump_udccr(x) do{}while(0)
  195. #define dump_udccs0(x) do{}while(0)
  196. #define dump_state(x) do{}while(0)
  197. #define UDC_DEBUG ((unsigned)0)
  198. #endif
  199. #define DBG(lvl, stuff...) do{if ((lvl) <= UDC_DEBUG) DMSG(stuff);}while(0)
  200. #define ERR(stuff...) pr_err("udc: " stuff)
  201. #define WARNING(stuff...) pr_warning("udc: " stuff)
  202. #define INFO(stuff...) pr_info("udc: " stuff)
  203. #endif /* __LINUX_USB_GADGET_PXA25X_H */