s3c2410_udc.c 48 KB

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  1. /*
  2. * linux/drivers/usb/gadget/s3c2410_udc.c
  3. *
  4. * Samsung S3C24xx series on-chip full speed USB device controllers
  5. *
  6. * Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
  7. * Additional cleanups by Ben Dooks <ben-linux@fluff.org>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #define pr_fmt(fmt) "s3c2410_udc: " fmt
  15. #include <linux/module.h>
  16. #include <linux/kernel.h>
  17. #include <linux/delay.h>
  18. #include <linux/ioport.h>
  19. #include <linux/sched.h>
  20. #include <linux/slab.h>
  21. #include <linux/errno.h>
  22. #include <linux/init.h>
  23. #include <linux/timer.h>
  24. #include <linux/list.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/clk.h>
  28. #include <linux/gpio.h>
  29. #include <linux/prefetch.h>
  30. #include <linux/io.h>
  31. #include <linux/debugfs.h>
  32. #include <linux/seq_file.h>
  33. #include <linux/usb.h>
  34. #include <linux/usb/gadget.h>
  35. #include <asm/byteorder.h>
  36. #include <asm/irq.h>
  37. #include <asm/unaligned.h>
  38. #include <mach/irqs.h>
  39. #include <mach/hardware.h>
  40. #include <plat/regs-udc.h>
  41. #include <linux/platform_data/usb-s3c2410_udc.h>
  42. #include "s3c2410_udc.h"
  43. #define DRIVER_DESC "S3C2410 USB Device Controller Gadget"
  44. #define DRIVER_VERSION "29 Apr 2007"
  45. #define DRIVER_AUTHOR "Herbert Pötzl <herbert@13thfloor.at>, " \
  46. "Arnaud Patard <arnaud.patard@rtp-net.org>"
  47. static const char gadget_name[] = "s3c2410_udc";
  48. static const char driver_desc[] = DRIVER_DESC;
  49. static struct s3c2410_udc *the_controller;
  50. static struct clk *udc_clock;
  51. static struct clk *usb_bus_clock;
  52. static void __iomem *base_addr;
  53. static u64 rsrc_start;
  54. static u64 rsrc_len;
  55. static struct dentry *s3c2410_udc_debugfs_root;
  56. static inline u32 udc_read(u32 reg)
  57. {
  58. return readb(base_addr + reg);
  59. }
  60. static inline void udc_write(u32 value, u32 reg)
  61. {
  62. writeb(value, base_addr + reg);
  63. }
  64. static inline void udc_writeb(void __iomem *base, u32 value, u32 reg)
  65. {
  66. writeb(value, base + reg);
  67. }
  68. static struct s3c2410_udc_mach_info *udc_info;
  69. /*************************** DEBUG FUNCTION ***************************/
  70. #define DEBUG_NORMAL 1
  71. #define DEBUG_VERBOSE 2
  72. #ifdef CONFIG_USB_S3C2410_DEBUG
  73. #define USB_S3C2410_DEBUG_LEVEL 0
  74. static uint32_t s3c2410_ticks = 0;
  75. __printf(2, 3)
  76. static void dprintk(int level, const char *fmt, ...)
  77. {
  78. static long prevticks;
  79. static int invocation;
  80. struct va_format vaf;
  81. va_list args;
  82. if (level > USB_S3C2410_DEBUG_LEVEL)
  83. return;
  84. va_start(args, fmt);
  85. vaf.fmt = fmt;
  86. vaf.va = &args;
  87. if (s3c2410_ticks != prevticks) {
  88. prevticks = s3c2410_ticks;
  89. invocation = 0;
  90. }
  91. pr_debug("%1lu.%02d USB: %pV", prevticks, invocation++, &vaf);
  92. va_end(args);
  93. }
  94. #else
  95. __printf(2, 3)
  96. static void dprintk(int level, const char *fmt, ...)
  97. {
  98. }
  99. #endif
  100. static int s3c2410_udc_debugfs_seq_show(struct seq_file *m, void *p)
  101. {
  102. u32 addr_reg, pwr_reg, ep_int_reg, usb_int_reg;
  103. u32 ep_int_en_reg, usb_int_en_reg, ep0_csr;
  104. u32 ep1_i_csr1, ep1_i_csr2, ep1_o_csr1, ep1_o_csr2;
  105. u32 ep2_i_csr1, ep2_i_csr2, ep2_o_csr1, ep2_o_csr2;
  106. addr_reg = udc_read(S3C2410_UDC_FUNC_ADDR_REG);
  107. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  108. ep_int_reg = udc_read(S3C2410_UDC_EP_INT_REG);
  109. usb_int_reg = udc_read(S3C2410_UDC_USB_INT_REG);
  110. ep_int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  111. usb_int_en_reg = udc_read(S3C2410_UDC_USB_INT_EN_REG);
  112. udc_write(0, S3C2410_UDC_INDEX_REG);
  113. ep0_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  114. udc_write(1, S3C2410_UDC_INDEX_REG);
  115. ep1_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  116. ep1_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  117. ep1_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  118. ep1_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  119. udc_write(2, S3C2410_UDC_INDEX_REG);
  120. ep2_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  121. ep2_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  122. ep2_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  123. ep2_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  124. seq_printf(m, "FUNC_ADDR_REG : 0x%04X\n"
  125. "PWR_REG : 0x%04X\n"
  126. "EP_INT_REG : 0x%04X\n"
  127. "USB_INT_REG : 0x%04X\n"
  128. "EP_INT_EN_REG : 0x%04X\n"
  129. "USB_INT_EN_REG : 0x%04X\n"
  130. "EP0_CSR : 0x%04X\n"
  131. "EP1_I_CSR1 : 0x%04X\n"
  132. "EP1_I_CSR2 : 0x%04X\n"
  133. "EP1_O_CSR1 : 0x%04X\n"
  134. "EP1_O_CSR2 : 0x%04X\n"
  135. "EP2_I_CSR1 : 0x%04X\n"
  136. "EP2_I_CSR2 : 0x%04X\n"
  137. "EP2_O_CSR1 : 0x%04X\n"
  138. "EP2_O_CSR2 : 0x%04X\n",
  139. addr_reg, pwr_reg, ep_int_reg, usb_int_reg,
  140. ep_int_en_reg, usb_int_en_reg, ep0_csr,
  141. ep1_i_csr1, ep1_i_csr2, ep1_o_csr1, ep1_o_csr2,
  142. ep2_i_csr1, ep2_i_csr2, ep2_o_csr1, ep2_o_csr2
  143. );
  144. return 0;
  145. }
  146. static int s3c2410_udc_debugfs_fops_open(struct inode *inode,
  147. struct file *file)
  148. {
  149. return single_open(file, s3c2410_udc_debugfs_seq_show, NULL);
  150. }
  151. static const struct file_operations s3c2410_udc_debugfs_fops = {
  152. .open = s3c2410_udc_debugfs_fops_open,
  153. .read = seq_read,
  154. .llseek = seq_lseek,
  155. .release = single_release,
  156. .owner = THIS_MODULE,
  157. };
  158. /* io macros */
  159. static inline void s3c2410_udc_clear_ep0_opr(void __iomem *base)
  160. {
  161. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  162. udc_writeb(base, S3C2410_UDC_EP0_CSR_SOPKTRDY,
  163. S3C2410_UDC_EP0_CSR_REG);
  164. }
  165. static inline void s3c2410_udc_clear_ep0_sst(void __iomem *base)
  166. {
  167. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  168. writeb(0x00, base + S3C2410_UDC_EP0_CSR_REG);
  169. }
  170. static inline void s3c2410_udc_clear_ep0_se(void __iomem *base)
  171. {
  172. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  173. udc_writeb(base, S3C2410_UDC_EP0_CSR_SSE, S3C2410_UDC_EP0_CSR_REG);
  174. }
  175. static inline void s3c2410_udc_set_ep0_ipr(void __iomem *base)
  176. {
  177. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  178. udc_writeb(base, S3C2410_UDC_EP0_CSR_IPKRDY, S3C2410_UDC_EP0_CSR_REG);
  179. }
  180. static inline void s3c2410_udc_set_ep0_de(void __iomem *base)
  181. {
  182. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  183. udc_writeb(base, S3C2410_UDC_EP0_CSR_DE, S3C2410_UDC_EP0_CSR_REG);
  184. }
  185. inline void s3c2410_udc_set_ep0_ss(void __iomem *b)
  186. {
  187. udc_writeb(b, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  188. udc_writeb(b, S3C2410_UDC_EP0_CSR_SENDSTL, S3C2410_UDC_EP0_CSR_REG);
  189. }
  190. static inline void s3c2410_udc_set_ep0_de_out(void __iomem *base)
  191. {
  192. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  193. udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
  194. | S3C2410_UDC_EP0_CSR_DE),
  195. S3C2410_UDC_EP0_CSR_REG);
  196. }
  197. static inline void s3c2410_udc_set_ep0_de_in(void __iomem *base)
  198. {
  199. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  200. udc_writeb(base, (S3C2410_UDC_EP0_CSR_IPKRDY
  201. | S3C2410_UDC_EP0_CSR_DE),
  202. S3C2410_UDC_EP0_CSR_REG);
  203. }
  204. /*------------------------- I/O ----------------------------------*/
  205. /*
  206. * s3c2410_udc_done
  207. */
  208. static void s3c2410_udc_done(struct s3c2410_ep *ep,
  209. struct s3c2410_request *req, int status)
  210. {
  211. unsigned halted = ep->halted;
  212. list_del_init(&req->queue);
  213. if (likely(req->req.status == -EINPROGRESS))
  214. req->req.status = status;
  215. else
  216. status = req->req.status;
  217. ep->halted = 1;
  218. usb_gadget_giveback_request(&ep->ep, &req->req);
  219. ep->halted = halted;
  220. }
  221. static void s3c2410_udc_nuke(struct s3c2410_udc *udc,
  222. struct s3c2410_ep *ep, int status)
  223. {
  224. /* Sanity check */
  225. if (&ep->queue == NULL)
  226. return;
  227. while (!list_empty(&ep->queue)) {
  228. struct s3c2410_request *req;
  229. req = list_entry(ep->queue.next, struct s3c2410_request,
  230. queue);
  231. s3c2410_udc_done(ep, req, status);
  232. }
  233. }
  234. static inline int s3c2410_udc_fifo_count_out(void)
  235. {
  236. int tmp;
  237. tmp = udc_read(S3C2410_UDC_OUT_FIFO_CNT2_REG) << 8;
  238. tmp |= udc_read(S3C2410_UDC_OUT_FIFO_CNT1_REG);
  239. return tmp;
  240. }
  241. /*
  242. * s3c2410_udc_write_packet
  243. */
  244. static inline int s3c2410_udc_write_packet(int fifo,
  245. struct s3c2410_request *req,
  246. unsigned max)
  247. {
  248. unsigned len = min(req->req.length - req->req.actual, max);
  249. u8 *buf = req->req.buf + req->req.actual;
  250. prefetch(buf);
  251. dprintk(DEBUG_VERBOSE, "%s %d %d %d %d\n", __func__,
  252. req->req.actual, req->req.length, len, req->req.actual + len);
  253. req->req.actual += len;
  254. udelay(5);
  255. writesb(base_addr + fifo, buf, len);
  256. return len;
  257. }
  258. /*
  259. * s3c2410_udc_write_fifo
  260. *
  261. * return: 0 = still running, 1 = completed, negative = errno
  262. */
  263. static int s3c2410_udc_write_fifo(struct s3c2410_ep *ep,
  264. struct s3c2410_request *req)
  265. {
  266. unsigned count;
  267. int is_last;
  268. u32 idx;
  269. int fifo_reg;
  270. u32 ep_csr;
  271. idx = ep->bEndpointAddress & 0x7F;
  272. switch (idx) {
  273. default:
  274. idx = 0;
  275. case 0:
  276. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  277. break;
  278. case 1:
  279. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  280. break;
  281. case 2:
  282. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  283. break;
  284. case 3:
  285. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  286. break;
  287. case 4:
  288. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  289. break;
  290. }
  291. count = s3c2410_udc_write_packet(fifo_reg, req, ep->ep.maxpacket);
  292. /* last packet is often short (sometimes a zlp) */
  293. if (count != ep->ep.maxpacket)
  294. is_last = 1;
  295. else if (req->req.length != req->req.actual || req->req.zero)
  296. is_last = 0;
  297. else
  298. is_last = 2;
  299. /* Only ep0 debug messages are interesting */
  300. if (idx == 0)
  301. dprintk(DEBUG_NORMAL,
  302. "Written ep%d %d.%d of %d b [last %d,z %d]\n",
  303. idx, count, req->req.actual, req->req.length,
  304. is_last, req->req.zero);
  305. if (is_last) {
  306. /* The order is important. It prevents sending 2 packets
  307. * at the same time */
  308. if (idx == 0) {
  309. /* Reset signal => no need to say 'data sent' */
  310. if (!(udc_read(S3C2410_UDC_USB_INT_REG)
  311. & S3C2410_UDC_USBINT_RESET))
  312. s3c2410_udc_set_ep0_de_in(base_addr);
  313. ep->dev->ep0state = EP0_IDLE;
  314. } else {
  315. udc_write(idx, S3C2410_UDC_INDEX_REG);
  316. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  317. udc_write(idx, S3C2410_UDC_INDEX_REG);
  318. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  319. S3C2410_UDC_IN_CSR1_REG);
  320. }
  321. s3c2410_udc_done(ep, req, 0);
  322. is_last = 1;
  323. } else {
  324. if (idx == 0) {
  325. /* Reset signal => no need to say 'data sent' */
  326. if (!(udc_read(S3C2410_UDC_USB_INT_REG)
  327. & S3C2410_UDC_USBINT_RESET))
  328. s3c2410_udc_set_ep0_ipr(base_addr);
  329. } else {
  330. udc_write(idx, S3C2410_UDC_INDEX_REG);
  331. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  332. udc_write(idx, S3C2410_UDC_INDEX_REG);
  333. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  334. S3C2410_UDC_IN_CSR1_REG);
  335. }
  336. }
  337. return is_last;
  338. }
  339. static inline int s3c2410_udc_read_packet(int fifo, u8 *buf,
  340. struct s3c2410_request *req, unsigned avail)
  341. {
  342. unsigned len;
  343. len = min(req->req.length - req->req.actual, avail);
  344. req->req.actual += len;
  345. readsb(fifo + base_addr, buf, len);
  346. return len;
  347. }
  348. /*
  349. * return: 0 = still running, 1 = queue empty, negative = errno
  350. */
  351. static int s3c2410_udc_read_fifo(struct s3c2410_ep *ep,
  352. struct s3c2410_request *req)
  353. {
  354. u8 *buf;
  355. u32 ep_csr;
  356. unsigned bufferspace;
  357. int is_last = 1;
  358. unsigned avail;
  359. int fifo_count = 0;
  360. u32 idx;
  361. int fifo_reg;
  362. idx = ep->bEndpointAddress & 0x7F;
  363. switch (idx) {
  364. default:
  365. idx = 0;
  366. case 0:
  367. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  368. break;
  369. case 1:
  370. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  371. break;
  372. case 2:
  373. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  374. break;
  375. case 3:
  376. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  377. break;
  378. case 4:
  379. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  380. break;
  381. }
  382. if (!req->req.length)
  383. return 1;
  384. buf = req->req.buf + req->req.actual;
  385. bufferspace = req->req.length - req->req.actual;
  386. if (!bufferspace) {
  387. dprintk(DEBUG_NORMAL, "%s: buffer full!\n", __func__);
  388. return -1;
  389. }
  390. udc_write(idx, S3C2410_UDC_INDEX_REG);
  391. fifo_count = s3c2410_udc_fifo_count_out();
  392. dprintk(DEBUG_NORMAL, "%s fifo count : %d\n", __func__, fifo_count);
  393. if (fifo_count > ep->ep.maxpacket)
  394. avail = ep->ep.maxpacket;
  395. else
  396. avail = fifo_count;
  397. fifo_count = s3c2410_udc_read_packet(fifo_reg, buf, req, avail);
  398. /* checking this with ep0 is not accurate as we already
  399. * read a control request
  400. **/
  401. if (idx != 0 && fifo_count < ep->ep.maxpacket) {
  402. is_last = 1;
  403. /* overflowed this request? flush extra data */
  404. if (fifo_count != avail)
  405. req->req.status = -EOVERFLOW;
  406. } else {
  407. is_last = (req->req.length <= req->req.actual) ? 1 : 0;
  408. }
  409. udc_write(idx, S3C2410_UDC_INDEX_REG);
  410. fifo_count = s3c2410_udc_fifo_count_out();
  411. /* Only ep0 debug messages are interesting */
  412. if (idx == 0)
  413. dprintk(DEBUG_VERBOSE, "%s fifo count : %d [last %d]\n",
  414. __func__, fifo_count, is_last);
  415. if (is_last) {
  416. if (idx == 0) {
  417. s3c2410_udc_set_ep0_de_out(base_addr);
  418. ep->dev->ep0state = EP0_IDLE;
  419. } else {
  420. udc_write(idx, S3C2410_UDC_INDEX_REG);
  421. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  422. udc_write(idx, S3C2410_UDC_INDEX_REG);
  423. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  424. S3C2410_UDC_OUT_CSR1_REG);
  425. }
  426. s3c2410_udc_done(ep, req, 0);
  427. } else {
  428. if (idx == 0) {
  429. s3c2410_udc_clear_ep0_opr(base_addr);
  430. } else {
  431. udc_write(idx, S3C2410_UDC_INDEX_REG);
  432. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  433. udc_write(idx, S3C2410_UDC_INDEX_REG);
  434. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  435. S3C2410_UDC_OUT_CSR1_REG);
  436. }
  437. }
  438. return is_last;
  439. }
  440. static int s3c2410_udc_read_fifo_crq(struct usb_ctrlrequest *crq)
  441. {
  442. unsigned char *outbuf = (unsigned char *)crq;
  443. int bytes_read = 0;
  444. udc_write(0, S3C2410_UDC_INDEX_REG);
  445. bytes_read = s3c2410_udc_fifo_count_out();
  446. dprintk(DEBUG_NORMAL, "%s: fifo_count=%d\n", __func__, bytes_read);
  447. if (bytes_read > sizeof(struct usb_ctrlrequest))
  448. bytes_read = sizeof(struct usb_ctrlrequest);
  449. readsb(S3C2410_UDC_EP0_FIFO_REG + base_addr, outbuf, bytes_read);
  450. dprintk(DEBUG_VERBOSE, "%s: len=%d %02x:%02x {%x,%x,%x}\n", __func__,
  451. bytes_read, crq->bRequest, crq->bRequestType,
  452. crq->wValue, crq->wIndex, crq->wLength);
  453. return bytes_read;
  454. }
  455. static int s3c2410_udc_get_status(struct s3c2410_udc *dev,
  456. struct usb_ctrlrequest *crq)
  457. {
  458. u16 status = 0;
  459. u8 ep_num = crq->wIndex & 0x7F;
  460. u8 is_in = crq->wIndex & USB_DIR_IN;
  461. switch (crq->bRequestType & USB_RECIP_MASK) {
  462. case USB_RECIP_INTERFACE:
  463. break;
  464. case USB_RECIP_DEVICE:
  465. status = dev->devstatus;
  466. break;
  467. case USB_RECIP_ENDPOINT:
  468. if (ep_num > 4 || crq->wLength > 2)
  469. return 1;
  470. if (ep_num == 0) {
  471. udc_write(0, S3C2410_UDC_INDEX_REG);
  472. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  473. status = status & S3C2410_UDC_EP0_CSR_SENDSTL;
  474. } else {
  475. udc_write(ep_num, S3C2410_UDC_INDEX_REG);
  476. if (is_in) {
  477. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  478. status = status & S3C2410_UDC_ICSR1_SENDSTL;
  479. } else {
  480. status = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  481. status = status & S3C2410_UDC_OCSR1_SENDSTL;
  482. }
  483. }
  484. status = status ? 1 : 0;
  485. break;
  486. default:
  487. return 1;
  488. }
  489. /* Seems to be needed to get it working. ouch :( */
  490. udelay(5);
  491. udc_write(status & 0xFF, S3C2410_UDC_EP0_FIFO_REG);
  492. udc_write(status >> 8, S3C2410_UDC_EP0_FIFO_REG);
  493. s3c2410_udc_set_ep0_de_in(base_addr);
  494. return 0;
  495. }
  496. /*------------------------- usb state machine -------------------------------*/
  497. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value);
  498. static void s3c2410_udc_handle_ep0_idle(struct s3c2410_udc *dev,
  499. struct s3c2410_ep *ep,
  500. struct usb_ctrlrequest *crq,
  501. u32 ep0csr)
  502. {
  503. int len, ret, tmp;
  504. /* start control request? */
  505. if (!(ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY))
  506. return;
  507. s3c2410_udc_nuke(dev, ep, -EPROTO);
  508. len = s3c2410_udc_read_fifo_crq(crq);
  509. if (len != sizeof(*crq)) {
  510. dprintk(DEBUG_NORMAL, "setup begin: fifo READ ERROR"
  511. " wanted %d bytes got %d. Stalling out...\n",
  512. sizeof(*crq), len);
  513. s3c2410_udc_set_ep0_ss(base_addr);
  514. return;
  515. }
  516. dprintk(DEBUG_NORMAL, "bRequest = %d bRequestType %d wLength = %d\n",
  517. crq->bRequest, crq->bRequestType, crq->wLength);
  518. /* cope with automagic for some standard requests. */
  519. dev->req_std = (crq->bRequestType & USB_TYPE_MASK)
  520. == USB_TYPE_STANDARD;
  521. dev->req_config = 0;
  522. dev->req_pending = 1;
  523. switch (crq->bRequest) {
  524. case USB_REQ_SET_CONFIGURATION:
  525. dprintk(DEBUG_NORMAL, "USB_REQ_SET_CONFIGURATION ...\n");
  526. if (crq->bRequestType == USB_RECIP_DEVICE) {
  527. dev->req_config = 1;
  528. s3c2410_udc_set_ep0_de_out(base_addr);
  529. }
  530. break;
  531. case USB_REQ_SET_INTERFACE:
  532. dprintk(DEBUG_NORMAL, "USB_REQ_SET_INTERFACE ...\n");
  533. if (crq->bRequestType == USB_RECIP_INTERFACE) {
  534. dev->req_config = 1;
  535. s3c2410_udc_set_ep0_de_out(base_addr);
  536. }
  537. break;
  538. case USB_REQ_SET_ADDRESS:
  539. dprintk(DEBUG_NORMAL, "USB_REQ_SET_ADDRESS ...\n");
  540. if (crq->bRequestType == USB_RECIP_DEVICE) {
  541. tmp = crq->wValue & 0x7F;
  542. dev->address = tmp;
  543. udc_write((tmp | S3C2410_UDC_FUNCADDR_UPDATE),
  544. S3C2410_UDC_FUNC_ADDR_REG);
  545. s3c2410_udc_set_ep0_de_out(base_addr);
  546. return;
  547. }
  548. break;
  549. case USB_REQ_GET_STATUS:
  550. dprintk(DEBUG_NORMAL, "USB_REQ_GET_STATUS ...\n");
  551. s3c2410_udc_clear_ep0_opr(base_addr);
  552. if (dev->req_std) {
  553. if (!s3c2410_udc_get_status(dev, crq))
  554. return;
  555. }
  556. break;
  557. case USB_REQ_CLEAR_FEATURE:
  558. s3c2410_udc_clear_ep0_opr(base_addr);
  559. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  560. break;
  561. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  562. break;
  563. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0);
  564. s3c2410_udc_set_ep0_de_out(base_addr);
  565. return;
  566. case USB_REQ_SET_FEATURE:
  567. s3c2410_udc_clear_ep0_opr(base_addr);
  568. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  569. break;
  570. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  571. break;
  572. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 1);
  573. s3c2410_udc_set_ep0_de_out(base_addr);
  574. return;
  575. default:
  576. s3c2410_udc_clear_ep0_opr(base_addr);
  577. break;
  578. }
  579. if (crq->bRequestType & USB_DIR_IN)
  580. dev->ep0state = EP0_IN_DATA_PHASE;
  581. else
  582. dev->ep0state = EP0_OUT_DATA_PHASE;
  583. if (!dev->driver)
  584. return;
  585. /* deliver the request to the gadget driver */
  586. ret = dev->driver->setup(&dev->gadget, crq);
  587. if (ret < 0) {
  588. if (dev->req_config) {
  589. dprintk(DEBUG_NORMAL, "config change %02x fail %d?\n",
  590. crq->bRequest, ret);
  591. return;
  592. }
  593. if (ret == -EOPNOTSUPP)
  594. dprintk(DEBUG_NORMAL, "Operation not supported\n");
  595. else
  596. dprintk(DEBUG_NORMAL,
  597. "dev->driver->setup failed. (%d)\n", ret);
  598. udelay(5);
  599. s3c2410_udc_set_ep0_ss(base_addr);
  600. s3c2410_udc_set_ep0_de_out(base_addr);
  601. dev->ep0state = EP0_IDLE;
  602. /* deferred i/o == no response yet */
  603. } else if (dev->req_pending) {
  604. dprintk(DEBUG_VERBOSE, "dev->req_pending... what now?\n");
  605. dev->req_pending = 0;
  606. }
  607. dprintk(DEBUG_VERBOSE, "ep0state %s\n", ep0states[dev->ep0state]);
  608. }
  609. static void s3c2410_udc_handle_ep0(struct s3c2410_udc *dev)
  610. {
  611. u32 ep0csr;
  612. struct s3c2410_ep *ep = &dev->ep[0];
  613. struct s3c2410_request *req;
  614. struct usb_ctrlrequest crq;
  615. if (list_empty(&ep->queue))
  616. req = NULL;
  617. else
  618. req = list_entry(ep->queue.next, struct s3c2410_request, queue);
  619. /* We make the assumption that S3C2410_UDC_IN_CSR1_REG equal to
  620. * S3C2410_UDC_EP0_CSR_REG when index is zero */
  621. udc_write(0, S3C2410_UDC_INDEX_REG);
  622. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  623. dprintk(DEBUG_NORMAL, "ep0csr %x ep0state %s\n",
  624. ep0csr, ep0states[dev->ep0state]);
  625. /* clear stall status */
  626. if (ep0csr & S3C2410_UDC_EP0_CSR_SENTSTL) {
  627. s3c2410_udc_nuke(dev, ep, -EPIPE);
  628. dprintk(DEBUG_NORMAL, "... clear SENT_STALL ...\n");
  629. s3c2410_udc_clear_ep0_sst(base_addr);
  630. dev->ep0state = EP0_IDLE;
  631. return;
  632. }
  633. /* clear setup end */
  634. if (ep0csr & S3C2410_UDC_EP0_CSR_SE) {
  635. dprintk(DEBUG_NORMAL, "... serviced SETUP_END ...\n");
  636. s3c2410_udc_nuke(dev, ep, 0);
  637. s3c2410_udc_clear_ep0_se(base_addr);
  638. dev->ep0state = EP0_IDLE;
  639. }
  640. switch (dev->ep0state) {
  641. case EP0_IDLE:
  642. s3c2410_udc_handle_ep0_idle(dev, ep, &crq, ep0csr);
  643. break;
  644. case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
  645. dprintk(DEBUG_NORMAL, "EP0_IN_DATA_PHASE ... what now?\n");
  646. if (!(ep0csr & S3C2410_UDC_EP0_CSR_IPKRDY) && req)
  647. s3c2410_udc_write_fifo(ep, req);
  648. break;
  649. case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
  650. dprintk(DEBUG_NORMAL, "EP0_OUT_DATA_PHASE ... what now?\n");
  651. if ((ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY) && req)
  652. s3c2410_udc_read_fifo(ep, req);
  653. break;
  654. case EP0_END_XFER:
  655. dprintk(DEBUG_NORMAL, "EP0_END_XFER ... what now?\n");
  656. dev->ep0state = EP0_IDLE;
  657. break;
  658. case EP0_STALL:
  659. dprintk(DEBUG_NORMAL, "EP0_STALL ... what now?\n");
  660. dev->ep0state = EP0_IDLE;
  661. break;
  662. }
  663. }
  664. /*
  665. * handle_ep - Manage I/O endpoints
  666. */
  667. static void s3c2410_udc_handle_ep(struct s3c2410_ep *ep)
  668. {
  669. struct s3c2410_request *req;
  670. int is_in = ep->bEndpointAddress & USB_DIR_IN;
  671. u32 ep_csr1;
  672. u32 idx;
  673. if (likely(!list_empty(&ep->queue)))
  674. req = list_entry(ep->queue.next,
  675. struct s3c2410_request, queue);
  676. else
  677. req = NULL;
  678. idx = ep->bEndpointAddress & 0x7F;
  679. if (is_in) {
  680. udc_write(idx, S3C2410_UDC_INDEX_REG);
  681. ep_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  682. dprintk(DEBUG_VERBOSE, "ep%01d write csr:%02x %d\n",
  683. idx, ep_csr1, req ? 1 : 0);
  684. if (ep_csr1 & S3C2410_UDC_ICSR1_SENTSTL) {
  685. dprintk(DEBUG_VERBOSE, "st\n");
  686. udc_write(idx, S3C2410_UDC_INDEX_REG);
  687. udc_write(ep_csr1 & ~S3C2410_UDC_ICSR1_SENTSTL,
  688. S3C2410_UDC_IN_CSR1_REG);
  689. return;
  690. }
  691. if (!(ep_csr1 & S3C2410_UDC_ICSR1_PKTRDY) && req)
  692. s3c2410_udc_write_fifo(ep, req);
  693. } else {
  694. udc_write(idx, S3C2410_UDC_INDEX_REG);
  695. ep_csr1 = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  696. dprintk(DEBUG_VERBOSE, "ep%01d rd csr:%02x\n", idx, ep_csr1);
  697. if (ep_csr1 & S3C2410_UDC_OCSR1_SENTSTL) {
  698. udc_write(idx, S3C2410_UDC_INDEX_REG);
  699. udc_write(ep_csr1 & ~S3C2410_UDC_OCSR1_SENTSTL,
  700. S3C2410_UDC_OUT_CSR1_REG);
  701. return;
  702. }
  703. if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req)
  704. s3c2410_udc_read_fifo(ep, req);
  705. }
  706. }
  707. #include <mach/regs-irq.h>
  708. /*
  709. * s3c2410_udc_irq - interrupt handler
  710. */
  711. static irqreturn_t s3c2410_udc_irq(int dummy, void *_dev)
  712. {
  713. struct s3c2410_udc *dev = _dev;
  714. int usb_status;
  715. int usbd_status;
  716. int pwr_reg;
  717. int ep0csr;
  718. int i;
  719. u32 idx, idx2;
  720. unsigned long flags;
  721. spin_lock_irqsave(&dev->lock, flags);
  722. /* Driver connected ? */
  723. if (!dev->driver) {
  724. /* Clear interrupts */
  725. udc_write(udc_read(S3C2410_UDC_USB_INT_REG),
  726. S3C2410_UDC_USB_INT_REG);
  727. udc_write(udc_read(S3C2410_UDC_EP_INT_REG),
  728. S3C2410_UDC_EP_INT_REG);
  729. }
  730. /* Save index */
  731. idx = udc_read(S3C2410_UDC_INDEX_REG);
  732. /* Read status registers */
  733. usb_status = udc_read(S3C2410_UDC_USB_INT_REG);
  734. usbd_status = udc_read(S3C2410_UDC_EP_INT_REG);
  735. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  736. udc_writeb(base_addr, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  737. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  738. dprintk(DEBUG_NORMAL, "usbs=%02x, usbds=%02x, pwr=%02x ep0csr=%02x\n",
  739. usb_status, usbd_status, pwr_reg, ep0csr);
  740. /*
  741. * Now, handle interrupts. There's two types :
  742. * - Reset, Resume, Suspend coming -> usb_int_reg
  743. * - EP -> ep_int_reg
  744. */
  745. /* RESET */
  746. if (usb_status & S3C2410_UDC_USBINT_RESET) {
  747. /* two kind of reset :
  748. * - reset start -> pwr reg = 8
  749. * - reset end -> pwr reg = 0
  750. **/
  751. dprintk(DEBUG_NORMAL, "USB reset csr %x pwr %x\n",
  752. ep0csr, pwr_reg);
  753. dev->gadget.speed = USB_SPEED_UNKNOWN;
  754. udc_write(0x00, S3C2410_UDC_INDEX_REG);
  755. udc_write((dev->ep[0].ep.maxpacket & 0x7ff) >> 3,
  756. S3C2410_UDC_MAXP_REG);
  757. dev->address = 0;
  758. dev->ep0state = EP0_IDLE;
  759. dev->gadget.speed = USB_SPEED_FULL;
  760. /* clear interrupt */
  761. udc_write(S3C2410_UDC_USBINT_RESET,
  762. S3C2410_UDC_USB_INT_REG);
  763. udc_write(idx, S3C2410_UDC_INDEX_REG);
  764. spin_unlock_irqrestore(&dev->lock, flags);
  765. return IRQ_HANDLED;
  766. }
  767. /* RESUME */
  768. if (usb_status & S3C2410_UDC_USBINT_RESUME) {
  769. dprintk(DEBUG_NORMAL, "USB resume\n");
  770. /* clear interrupt */
  771. udc_write(S3C2410_UDC_USBINT_RESUME,
  772. S3C2410_UDC_USB_INT_REG);
  773. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  774. && dev->driver
  775. && dev->driver->resume)
  776. dev->driver->resume(&dev->gadget);
  777. }
  778. /* SUSPEND */
  779. if (usb_status & S3C2410_UDC_USBINT_SUSPEND) {
  780. dprintk(DEBUG_NORMAL, "USB suspend\n");
  781. /* clear interrupt */
  782. udc_write(S3C2410_UDC_USBINT_SUSPEND,
  783. S3C2410_UDC_USB_INT_REG);
  784. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  785. && dev->driver
  786. && dev->driver->suspend)
  787. dev->driver->suspend(&dev->gadget);
  788. dev->ep0state = EP0_IDLE;
  789. }
  790. /* EP */
  791. /* control traffic */
  792. /* check on ep0csr != 0 is not a good idea as clearing in_pkt_ready
  793. * generate an interrupt
  794. */
  795. if (usbd_status & S3C2410_UDC_INT_EP0) {
  796. dprintk(DEBUG_VERBOSE, "USB ep0 irq\n");
  797. /* Clear the interrupt bit by setting it to 1 */
  798. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_REG);
  799. s3c2410_udc_handle_ep0(dev);
  800. }
  801. /* endpoint data transfers */
  802. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  803. u32 tmp = 1 << i;
  804. if (usbd_status & tmp) {
  805. dprintk(DEBUG_VERBOSE, "USB ep%d irq\n", i);
  806. /* Clear the interrupt bit by setting it to 1 */
  807. udc_write(tmp, S3C2410_UDC_EP_INT_REG);
  808. s3c2410_udc_handle_ep(&dev->ep[i]);
  809. }
  810. }
  811. /* what else causes this interrupt? a receive! who is it? */
  812. if (!usb_status && !usbd_status && !pwr_reg && !ep0csr) {
  813. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  814. idx2 = udc_read(S3C2410_UDC_INDEX_REG);
  815. udc_write(i, S3C2410_UDC_INDEX_REG);
  816. if (udc_read(S3C2410_UDC_OUT_CSR1_REG) & 0x1)
  817. s3c2410_udc_handle_ep(&dev->ep[i]);
  818. /* restore index */
  819. udc_write(idx2, S3C2410_UDC_INDEX_REG);
  820. }
  821. }
  822. dprintk(DEBUG_VERBOSE, "irq: %d s3c2410_udc_done.\n", IRQ_USBD);
  823. /* Restore old index */
  824. udc_write(idx, S3C2410_UDC_INDEX_REG);
  825. spin_unlock_irqrestore(&dev->lock, flags);
  826. return IRQ_HANDLED;
  827. }
  828. /*------------------------- s3c2410_ep_ops ----------------------------------*/
  829. static inline struct s3c2410_ep *to_s3c2410_ep(struct usb_ep *ep)
  830. {
  831. return container_of(ep, struct s3c2410_ep, ep);
  832. }
  833. static inline struct s3c2410_udc *to_s3c2410_udc(struct usb_gadget *gadget)
  834. {
  835. return container_of(gadget, struct s3c2410_udc, gadget);
  836. }
  837. static inline struct s3c2410_request *to_s3c2410_req(struct usb_request *req)
  838. {
  839. return container_of(req, struct s3c2410_request, req);
  840. }
  841. /*
  842. * s3c2410_udc_ep_enable
  843. */
  844. static int s3c2410_udc_ep_enable(struct usb_ep *_ep,
  845. const struct usb_endpoint_descriptor *desc)
  846. {
  847. struct s3c2410_udc *dev;
  848. struct s3c2410_ep *ep;
  849. u32 max, tmp;
  850. unsigned long flags;
  851. u32 csr1, csr2;
  852. u32 int_en_reg;
  853. ep = to_s3c2410_ep(_ep);
  854. if (!_ep || !desc
  855. || _ep->name == ep0name
  856. || desc->bDescriptorType != USB_DT_ENDPOINT)
  857. return -EINVAL;
  858. dev = ep->dev;
  859. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  860. return -ESHUTDOWN;
  861. max = usb_endpoint_maxp(desc) & 0x1fff;
  862. local_irq_save(flags);
  863. _ep->maxpacket = max & 0x7ff;
  864. ep->ep.desc = desc;
  865. ep->halted = 0;
  866. ep->bEndpointAddress = desc->bEndpointAddress;
  867. /* set max packet */
  868. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  869. udc_write(max >> 3, S3C2410_UDC_MAXP_REG);
  870. /* set type, direction, address; reset fifo counters */
  871. if (desc->bEndpointAddress & USB_DIR_IN) {
  872. csr1 = S3C2410_UDC_ICSR1_FFLUSH|S3C2410_UDC_ICSR1_CLRDT;
  873. csr2 = S3C2410_UDC_ICSR2_MODEIN|S3C2410_UDC_ICSR2_DMAIEN;
  874. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  875. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  876. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  877. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  878. } else {
  879. /* don't flush in fifo or it will cause endpoint interrupt */
  880. csr1 = S3C2410_UDC_ICSR1_CLRDT;
  881. csr2 = S3C2410_UDC_ICSR2_DMAIEN;
  882. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  883. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  884. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  885. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  886. csr1 = S3C2410_UDC_OCSR1_FFLUSH | S3C2410_UDC_OCSR1_CLRDT;
  887. csr2 = S3C2410_UDC_OCSR2_DMAIEN;
  888. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  889. udc_write(csr1, S3C2410_UDC_OUT_CSR1_REG);
  890. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  891. udc_write(csr2, S3C2410_UDC_OUT_CSR2_REG);
  892. }
  893. /* enable irqs */
  894. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  895. udc_write(int_en_reg | (1 << ep->num), S3C2410_UDC_EP_INT_EN_REG);
  896. /* print some debug message */
  897. tmp = desc->bEndpointAddress;
  898. dprintk(DEBUG_NORMAL, "enable %s(%d) ep%x%s-blk max %02x\n",
  899. _ep->name, ep->num, tmp,
  900. desc->bEndpointAddress & USB_DIR_IN ? "in" : "out", max);
  901. local_irq_restore(flags);
  902. s3c2410_udc_set_halt(_ep, 0);
  903. return 0;
  904. }
  905. /*
  906. * s3c2410_udc_ep_disable
  907. */
  908. static int s3c2410_udc_ep_disable(struct usb_ep *_ep)
  909. {
  910. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  911. unsigned long flags;
  912. u32 int_en_reg;
  913. if (!_ep || !ep->ep.desc) {
  914. dprintk(DEBUG_NORMAL, "%s not enabled\n",
  915. _ep ? ep->ep.name : NULL);
  916. return -EINVAL;
  917. }
  918. local_irq_save(flags);
  919. dprintk(DEBUG_NORMAL, "ep_disable: %s\n", _ep->name);
  920. ep->ep.desc = NULL;
  921. ep->halted = 1;
  922. s3c2410_udc_nuke(ep->dev, ep, -ESHUTDOWN);
  923. /* disable irqs */
  924. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  925. udc_write(int_en_reg & ~(1<<ep->num), S3C2410_UDC_EP_INT_EN_REG);
  926. local_irq_restore(flags);
  927. dprintk(DEBUG_NORMAL, "%s disabled\n", _ep->name);
  928. return 0;
  929. }
  930. /*
  931. * s3c2410_udc_alloc_request
  932. */
  933. static struct usb_request *
  934. s3c2410_udc_alloc_request(struct usb_ep *_ep, gfp_t mem_flags)
  935. {
  936. struct s3c2410_request *req;
  937. dprintk(DEBUG_VERBOSE, "%s(%p,%d)\n", __func__, _ep, mem_flags);
  938. if (!_ep)
  939. return NULL;
  940. req = kzalloc(sizeof(struct s3c2410_request), mem_flags);
  941. if (!req)
  942. return NULL;
  943. INIT_LIST_HEAD(&req->queue);
  944. return &req->req;
  945. }
  946. /*
  947. * s3c2410_udc_free_request
  948. */
  949. static void
  950. s3c2410_udc_free_request(struct usb_ep *_ep, struct usb_request *_req)
  951. {
  952. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  953. struct s3c2410_request *req = to_s3c2410_req(_req);
  954. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  955. if (!ep || !_req || (!ep->ep.desc && _ep->name != ep0name))
  956. return;
  957. WARN_ON(!list_empty(&req->queue));
  958. kfree(req);
  959. }
  960. /*
  961. * s3c2410_udc_queue
  962. */
  963. static int s3c2410_udc_queue(struct usb_ep *_ep, struct usb_request *_req,
  964. gfp_t gfp_flags)
  965. {
  966. struct s3c2410_request *req = to_s3c2410_req(_req);
  967. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  968. struct s3c2410_udc *dev;
  969. u32 ep_csr = 0;
  970. int fifo_count = 0;
  971. unsigned long flags;
  972. if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
  973. dprintk(DEBUG_NORMAL, "%s: invalid args\n", __func__);
  974. return -EINVAL;
  975. }
  976. dev = ep->dev;
  977. if (unlikely(!dev->driver
  978. || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
  979. return -ESHUTDOWN;
  980. }
  981. local_irq_save(flags);
  982. if (unlikely(!_req || !_req->complete
  983. || !_req->buf || !list_empty(&req->queue))) {
  984. if (!_req)
  985. dprintk(DEBUG_NORMAL, "%s: 1 X X X\n", __func__);
  986. else {
  987. dprintk(DEBUG_NORMAL, "%s: 0 %01d %01d %01d\n",
  988. __func__, !_req->complete, !_req->buf,
  989. !list_empty(&req->queue));
  990. }
  991. local_irq_restore(flags);
  992. return -EINVAL;
  993. }
  994. _req->status = -EINPROGRESS;
  995. _req->actual = 0;
  996. dprintk(DEBUG_VERBOSE, "%s: ep%x len %d\n",
  997. __func__, ep->bEndpointAddress, _req->length);
  998. if (ep->bEndpointAddress) {
  999. udc_write(ep->bEndpointAddress & 0x7F, S3C2410_UDC_INDEX_REG);
  1000. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  1001. ? S3C2410_UDC_IN_CSR1_REG
  1002. : S3C2410_UDC_OUT_CSR1_REG);
  1003. fifo_count = s3c2410_udc_fifo_count_out();
  1004. } else {
  1005. udc_write(0, S3C2410_UDC_INDEX_REG);
  1006. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  1007. fifo_count = s3c2410_udc_fifo_count_out();
  1008. }
  1009. /* kickstart this i/o queue? */
  1010. if (list_empty(&ep->queue) && !ep->halted) {
  1011. if (ep->bEndpointAddress == 0 /* ep0 */) {
  1012. switch (dev->ep0state) {
  1013. case EP0_IN_DATA_PHASE:
  1014. if (!(ep_csr&S3C2410_UDC_EP0_CSR_IPKRDY)
  1015. && s3c2410_udc_write_fifo(ep,
  1016. req)) {
  1017. dev->ep0state = EP0_IDLE;
  1018. req = NULL;
  1019. }
  1020. break;
  1021. case EP0_OUT_DATA_PHASE:
  1022. if ((!_req->length)
  1023. || ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1024. && s3c2410_udc_read_fifo(ep,
  1025. req))) {
  1026. dev->ep0state = EP0_IDLE;
  1027. req = NULL;
  1028. }
  1029. break;
  1030. default:
  1031. local_irq_restore(flags);
  1032. return -EL2HLT;
  1033. }
  1034. } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
  1035. && (!(ep_csr&S3C2410_UDC_OCSR1_PKTRDY))
  1036. && s3c2410_udc_write_fifo(ep, req)) {
  1037. req = NULL;
  1038. } else if ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1039. && fifo_count
  1040. && s3c2410_udc_read_fifo(ep, req)) {
  1041. req = NULL;
  1042. }
  1043. }
  1044. /* pio or dma irq handler advances the queue. */
  1045. if (likely(req))
  1046. list_add_tail(&req->queue, &ep->queue);
  1047. local_irq_restore(flags);
  1048. dprintk(DEBUG_VERBOSE, "%s ok\n", __func__);
  1049. return 0;
  1050. }
  1051. /*
  1052. * s3c2410_udc_dequeue
  1053. */
  1054. static int s3c2410_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1055. {
  1056. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1057. struct s3c2410_udc *udc;
  1058. int retval = -EINVAL;
  1059. unsigned long flags;
  1060. struct s3c2410_request *req = NULL;
  1061. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  1062. if (!the_controller->driver)
  1063. return -ESHUTDOWN;
  1064. if (!_ep || !_req)
  1065. return retval;
  1066. udc = to_s3c2410_udc(ep->gadget);
  1067. local_irq_save(flags);
  1068. list_for_each_entry(req, &ep->queue, queue) {
  1069. if (&req->req == _req) {
  1070. list_del_init(&req->queue);
  1071. _req->status = -ECONNRESET;
  1072. retval = 0;
  1073. break;
  1074. }
  1075. }
  1076. if (retval == 0) {
  1077. dprintk(DEBUG_VERBOSE,
  1078. "dequeued req %p from %s, len %d buf %p\n",
  1079. req, _ep->name, _req->length, _req->buf);
  1080. s3c2410_udc_done(ep, req, -ECONNRESET);
  1081. }
  1082. local_irq_restore(flags);
  1083. return retval;
  1084. }
  1085. /*
  1086. * s3c2410_udc_set_halt
  1087. */
  1088. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value)
  1089. {
  1090. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1091. u32 ep_csr = 0;
  1092. unsigned long flags;
  1093. u32 idx;
  1094. if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
  1095. dprintk(DEBUG_NORMAL, "%s: inval 2\n", __func__);
  1096. return -EINVAL;
  1097. }
  1098. local_irq_save(flags);
  1099. idx = ep->bEndpointAddress & 0x7F;
  1100. if (idx == 0) {
  1101. s3c2410_udc_set_ep0_ss(base_addr);
  1102. s3c2410_udc_set_ep0_de_out(base_addr);
  1103. } else {
  1104. udc_write(idx, S3C2410_UDC_INDEX_REG);
  1105. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  1106. ? S3C2410_UDC_IN_CSR1_REG
  1107. : S3C2410_UDC_OUT_CSR1_REG);
  1108. if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
  1109. if (value)
  1110. udc_write(ep_csr | S3C2410_UDC_ICSR1_SENDSTL,
  1111. S3C2410_UDC_IN_CSR1_REG);
  1112. else {
  1113. ep_csr &= ~S3C2410_UDC_ICSR1_SENDSTL;
  1114. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1115. ep_csr |= S3C2410_UDC_ICSR1_CLRDT;
  1116. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1117. }
  1118. } else {
  1119. if (value)
  1120. udc_write(ep_csr | S3C2410_UDC_OCSR1_SENDSTL,
  1121. S3C2410_UDC_OUT_CSR1_REG);
  1122. else {
  1123. ep_csr &= ~S3C2410_UDC_OCSR1_SENDSTL;
  1124. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1125. ep_csr |= S3C2410_UDC_OCSR1_CLRDT;
  1126. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1127. }
  1128. }
  1129. }
  1130. ep->halted = value ? 1 : 0;
  1131. local_irq_restore(flags);
  1132. return 0;
  1133. }
  1134. static const struct usb_ep_ops s3c2410_ep_ops = {
  1135. .enable = s3c2410_udc_ep_enable,
  1136. .disable = s3c2410_udc_ep_disable,
  1137. .alloc_request = s3c2410_udc_alloc_request,
  1138. .free_request = s3c2410_udc_free_request,
  1139. .queue = s3c2410_udc_queue,
  1140. .dequeue = s3c2410_udc_dequeue,
  1141. .set_halt = s3c2410_udc_set_halt,
  1142. };
  1143. /*------------------------- usb_gadget_ops ----------------------------------*/
  1144. /*
  1145. * s3c2410_udc_get_frame
  1146. */
  1147. static int s3c2410_udc_get_frame(struct usb_gadget *_gadget)
  1148. {
  1149. int tmp;
  1150. dprintk(DEBUG_VERBOSE, "%s()\n", __func__);
  1151. tmp = udc_read(S3C2410_UDC_FRAME_NUM2_REG) << 8;
  1152. tmp |= udc_read(S3C2410_UDC_FRAME_NUM1_REG);
  1153. return tmp;
  1154. }
  1155. /*
  1156. * s3c2410_udc_wakeup
  1157. */
  1158. static int s3c2410_udc_wakeup(struct usb_gadget *_gadget)
  1159. {
  1160. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1161. return 0;
  1162. }
  1163. /*
  1164. * s3c2410_udc_set_selfpowered
  1165. */
  1166. static int s3c2410_udc_set_selfpowered(struct usb_gadget *gadget, int value)
  1167. {
  1168. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1169. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1170. gadget->is_selfpowered = (value != 0);
  1171. if (value)
  1172. udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED);
  1173. else
  1174. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  1175. return 0;
  1176. }
  1177. static void s3c2410_udc_disable(struct s3c2410_udc *dev);
  1178. static void s3c2410_udc_enable(struct s3c2410_udc *dev);
  1179. static int s3c2410_udc_set_pullup(struct s3c2410_udc *udc, int is_on)
  1180. {
  1181. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1182. if (udc_info && (udc_info->udc_command ||
  1183. gpio_is_valid(udc_info->pullup_pin))) {
  1184. if (is_on)
  1185. s3c2410_udc_enable(udc);
  1186. else {
  1187. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1188. if (udc->driver && udc->driver->disconnect)
  1189. udc->driver->disconnect(&udc->gadget);
  1190. }
  1191. s3c2410_udc_disable(udc);
  1192. }
  1193. } else {
  1194. return -EOPNOTSUPP;
  1195. }
  1196. return 0;
  1197. }
  1198. static int s3c2410_udc_vbus_session(struct usb_gadget *gadget, int is_active)
  1199. {
  1200. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1201. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1202. udc->vbus = (is_active != 0);
  1203. s3c2410_udc_set_pullup(udc, is_active);
  1204. return 0;
  1205. }
  1206. static int s3c2410_udc_pullup(struct usb_gadget *gadget, int is_on)
  1207. {
  1208. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1209. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1210. s3c2410_udc_set_pullup(udc, is_on);
  1211. return 0;
  1212. }
  1213. static irqreturn_t s3c2410_udc_vbus_irq(int irq, void *_dev)
  1214. {
  1215. struct s3c2410_udc *dev = _dev;
  1216. unsigned int value;
  1217. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1218. value = gpio_get_value(udc_info->vbus_pin) ? 1 : 0;
  1219. if (udc_info->vbus_pin_inverted)
  1220. value = !value;
  1221. if (value != dev->vbus)
  1222. s3c2410_udc_vbus_session(&dev->gadget, value);
  1223. return IRQ_HANDLED;
  1224. }
  1225. static int s3c2410_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1226. {
  1227. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1228. if (udc_info && udc_info->vbus_draw) {
  1229. udc_info->vbus_draw(ma);
  1230. return 0;
  1231. }
  1232. return -ENOTSUPP;
  1233. }
  1234. static int s3c2410_udc_start(struct usb_gadget *g,
  1235. struct usb_gadget_driver *driver);
  1236. static int s3c2410_udc_stop(struct usb_gadget *g);
  1237. static const struct usb_gadget_ops s3c2410_ops = {
  1238. .get_frame = s3c2410_udc_get_frame,
  1239. .wakeup = s3c2410_udc_wakeup,
  1240. .set_selfpowered = s3c2410_udc_set_selfpowered,
  1241. .pullup = s3c2410_udc_pullup,
  1242. .vbus_session = s3c2410_udc_vbus_session,
  1243. .vbus_draw = s3c2410_vbus_draw,
  1244. .udc_start = s3c2410_udc_start,
  1245. .udc_stop = s3c2410_udc_stop,
  1246. };
  1247. static void s3c2410_udc_command(enum s3c2410_udc_cmd_e cmd)
  1248. {
  1249. if (!udc_info)
  1250. return;
  1251. if (udc_info->udc_command) {
  1252. udc_info->udc_command(cmd);
  1253. } else if (gpio_is_valid(udc_info->pullup_pin)) {
  1254. int value;
  1255. switch (cmd) {
  1256. case S3C2410_UDC_P_ENABLE:
  1257. value = 1;
  1258. break;
  1259. case S3C2410_UDC_P_DISABLE:
  1260. value = 0;
  1261. break;
  1262. default:
  1263. return;
  1264. }
  1265. value ^= udc_info->pullup_pin_inverted;
  1266. gpio_set_value(udc_info->pullup_pin, value);
  1267. }
  1268. }
  1269. /*------------------------- gadget driver handling---------------------------*/
  1270. /*
  1271. * s3c2410_udc_disable
  1272. */
  1273. static void s3c2410_udc_disable(struct s3c2410_udc *dev)
  1274. {
  1275. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1276. /* Disable all interrupts */
  1277. udc_write(0x00, S3C2410_UDC_USB_INT_EN_REG);
  1278. udc_write(0x00, S3C2410_UDC_EP_INT_EN_REG);
  1279. /* Clear the interrupt registers */
  1280. udc_write(S3C2410_UDC_USBINT_RESET
  1281. | S3C2410_UDC_USBINT_RESUME
  1282. | S3C2410_UDC_USBINT_SUSPEND,
  1283. S3C2410_UDC_USB_INT_REG);
  1284. udc_write(0x1F, S3C2410_UDC_EP_INT_REG);
  1285. /* Good bye, cruel world */
  1286. s3c2410_udc_command(S3C2410_UDC_P_DISABLE);
  1287. /* Set speed to unknown */
  1288. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1289. }
  1290. /*
  1291. * s3c2410_udc_reinit
  1292. */
  1293. static void s3c2410_udc_reinit(struct s3c2410_udc *dev)
  1294. {
  1295. u32 i;
  1296. /* device/ep0 records init */
  1297. INIT_LIST_HEAD(&dev->gadget.ep_list);
  1298. INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
  1299. dev->ep0state = EP0_IDLE;
  1300. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1301. struct s3c2410_ep *ep = &dev->ep[i];
  1302. if (i != 0)
  1303. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  1304. ep->dev = dev;
  1305. ep->ep.desc = NULL;
  1306. ep->halted = 0;
  1307. INIT_LIST_HEAD(&ep->queue);
  1308. usb_ep_set_maxpacket_limit(&ep->ep, ep->ep.maxpacket);
  1309. }
  1310. }
  1311. /*
  1312. * s3c2410_udc_enable
  1313. */
  1314. static void s3c2410_udc_enable(struct s3c2410_udc *dev)
  1315. {
  1316. int i;
  1317. dprintk(DEBUG_NORMAL, "s3c2410_udc_enable called\n");
  1318. /* dev->gadget.speed = USB_SPEED_UNKNOWN; */
  1319. dev->gadget.speed = USB_SPEED_FULL;
  1320. /* Set MAXP for all endpoints */
  1321. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1322. udc_write(i, S3C2410_UDC_INDEX_REG);
  1323. udc_write((dev->ep[i].ep.maxpacket & 0x7ff) >> 3,
  1324. S3C2410_UDC_MAXP_REG);
  1325. }
  1326. /* Set default power state */
  1327. udc_write(DEFAULT_POWER_STATE, S3C2410_UDC_PWR_REG);
  1328. /* Enable reset and suspend interrupt interrupts */
  1329. udc_write(S3C2410_UDC_USBINT_RESET | S3C2410_UDC_USBINT_SUSPEND,
  1330. S3C2410_UDC_USB_INT_EN_REG);
  1331. /* Enable ep0 interrupt */
  1332. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_EN_REG);
  1333. /* time to say "hello, world" */
  1334. s3c2410_udc_command(S3C2410_UDC_P_ENABLE);
  1335. }
  1336. static int s3c2410_udc_start(struct usb_gadget *g,
  1337. struct usb_gadget_driver *driver)
  1338. {
  1339. struct s3c2410_udc *udc = to_s3c2410(g);
  1340. dprintk(DEBUG_NORMAL, "%s() '%s'\n", __func__, driver->driver.name);
  1341. /* Hook the driver */
  1342. udc->driver = driver;
  1343. /* Enable udc */
  1344. s3c2410_udc_enable(udc);
  1345. return 0;
  1346. }
  1347. static int s3c2410_udc_stop(struct usb_gadget *g)
  1348. {
  1349. struct s3c2410_udc *udc = to_s3c2410(g);
  1350. udc->driver = NULL;
  1351. /* Disable udc */
  1352. s3c2410_udc_disable(udc);
  1353. return 0;
  1354. }
  1355. /*---------------------------------------------------------------------------*/
  1356. static struct s3c2410_udc memory = {
  1357. .gadget = {
  1358. .ops = &s3c2410_ops,
  1359. .ep0 = &memory.ep[0].ep,
  1360. .name = gadget_name,
  1361. .dev = {
  1362. .init_name = "gadget",
  1363. },
  1364. },
  1365. /* control endpoint */
  1366. .ep[0] = {
  1367. .num = 0,
  1368. .ep = {
  1369. .name = ep0name,
  1370. .ops = &s3c2410_ep_ops,
  1371. .maxpacket = EP0_FIFO_SIZE,
  1372. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
  1373. USB_EP_CAPS_DIR_ALL),
  1374. },
  1375. .dev = &memory,
  1376. },
  1377. /* first group of endpoints */
  1378. .ep[1] = {
  1379. .num = 1,
  1380. .ep = {
  1381. .name = "ep1-bulk",
  1382. .ops = &s3c2410_ep_ops,
  1383. .maxpacket = EP_FIFO_SIZE,
  1384. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  1385. USB_EP_CAPS_DIR_ALL),
  1386. },
  1387. .dev = &memory,
  1388. .fifo_size = EP_FIFO_SIZE,
  1389. .bEndpointAddress = 1,
  1390. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1391. },
  1392. .ep[2] = {
  1393. .num = 2,
  1394. .ep = {
  1395. .name = "ep2-bulk",
  1396. .ops = &s3c2410_ep_ops,
  1397. .maxpacket = EP_FIFO_SIZE,
  1398. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  1399. USB_EP_CAPS_DIR_ALL),
  1400. },
  1401. .dev = &memory,
  1402. .fifo_size = EP_FIFO_SIZE,
  1403. .bEndpointAddress = 2,
  1404. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1405. },
  1406. .ep[3] = {
  1407. .num = 3,
  1408. .ep = {
  1409. .name = "ep3-bulk",
  1410. .ops = &s3c2410_ep_ops,
  1411. .maxpacket = EP_FIFO_SIZE,
  1412. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  1413. USB_EP_CAPS_DIR_ALL),
  1414. },
  1415. .dev = &memory,
  1416. .fifo_size = EP_FIFO_SIZE,
  1417. .bEndpointAddress = 3,
  1418. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1419. },
  1420. .ep[4] = {
  1421. .num = 4,
  1422. .ep = {
  1423. .name = "ep4-bulk",
  1424. .ops = &s3c2410_ep_ops,
  1425. .maxpacket = EP_FIFO_SIZE,
  1426. .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
  1427. USB_EP_CAPS_DIR_ALL),
  1428. },
  1429. .dev = &memory,
  1430. .fifo_size = EP_FIFO_SIZE,
  1431. .bEndpointAddress = 4,
  1432. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1433. }
  1434. };
  1435. /*
  1436. * probe - binds to the platform device
  1437. */
  1438. static int s3c2410_udc_probe(struct platform_device *pdev)
  1439. {
  1440. struct s3c2410_udc *udc = &memory;
  1441. struct device *dev = &pdev->dev;
  1442. int retval;
  1443. int irq;
  1444. dev_dbg(dev, "%s()\n", __func__);
  1445. usb_bus_clock = clk_get(NULL, "usb-bus-gadget");
  1446. if (IS_ERR(usb_bus_clock)) {
  1447. dev_err(dev, "failed to get usb bus clock source\n");
  1448. return PTR_ERR(usb_bus_clock);
  1449. }
  1450. clk_prepare_enable(usb_bus_clock);
  1451. udc_clock = clk_get(NULL, "usb-device");
  1452. if (IS_ERR(udc_clock)) {
  1453. dev_err(dev, "failed to get udc clock source\n");
  1454. return PTR_ERR(udc_clock);
  1455. }
  1456. clk_prepare_enable(udc_clock);
  1457. mdelay(10);
  1458. dev_dbg(dev, "got and enabled clocks\n");
  1459. if (strncmp(pdev->name, "s3c2440", 7) == 0) {
  1460. dev_info(dev, "S3C2440: increasing FIFO to 128 bytes\n");
  1461. memory.ep[1].fifo_size = S3C2440_EP_FIFO_SIZE;
  1462. memory.ep[2].fifo_size = S3C2440_EP_FIFO_SIZE;
  1463. memory.ep[3].fifo_size = S3C2440_EP_FIFO_SIZE;
  1464. memory.ep[4].fifo_size = S3C2440_EP_FIFO_SIZE;
  1465. }
  1466. spin_lock_init(&udc->lock);
  1467. udc_info = dev_get_platdata(&pdev->dev);
  1468. rsrc_start = S3C2410_PA_USBDEV;
  1469. rsrc_len = S3C24XX_SZ_USBDEV;
  1470. if (!request_mem_region(rsrc_start, rsrc_len, gadget_name))
  1471. return -EBUSY;
  1472. base_addr = ioremap(rsrc_start, rsrc_len);
  1473. if (!base_addr) {
  1474. retval = -ENOMEM;
  1475. goto err_mem;
  1476. }
  1477. the_controller = udc;
  1478. platform_set_drvdata(pdev, udc);
  1479. s3c2410_udc_disable(udc);
  1480. s3c2410_udc_reinit(udc);
  1481. /* irq setup after old hardware state is cleaned up */
  1482. retval = request_irq(IRQ_USBD, s3c2410_udc_irq,
  1483. 0, gadget_name, udc);
  1484. if (retval != 0) {
  1485. dev_err(dev, "cannot get irq %i, err %d\n", IRQ_USBD, retval);
  1486. retval = -EBUSY;
  1487. goto err_map;
  1488. }
  1489. dev_dbg(dev, "got irq %i\n", IRQ_USBD);
  1490. if (udc_info && udc_info->vbus_pin > 0) {
  1491. retval = gpio_request(udc_info->vbus_pin, "udc vbus");
  1492. if (retval < 0) {
  1493. dev_err(dev, "cannot claim vbus pin\n");
  1494. goto err_int;
  1495. }
  1496. irq = gpio_to_irq(udc_info->vbus_pin);
  1497. if (irq < 0) {
  1498. dev_err(dev, "no irq for gpio vbus pin\n");
  1499. retval = irq;
  1500. goto err_gpio_claim;
  1501. }
  1502. retval = request_irq(irq, s3c2410_udc_vbus_irq,
  1503. IRQF_TRIGGER_RISING
  1504. | IRQF_TRIGGER_FALLING | IRQF_SHARED,
  1505. gadget_name, udc);
  1506. if (retval != 0) {
  1507. dev_err(dev, "can't get vbus irq %d, err %d\n",
  1508. irq, retval);
  1509. retval = -EBUSY;
  1510. goto err_gpio_claim;
  1511. }
  1512. dev_dbg(dev, "got irq %i\n", irq);
  1513. } else {
  1514. udc->vbus = 1;
  1515. }
  1516. if (udc_info && !udc_info->udc_command &&
  1517. gpio_is_valid(udc_info->pullup_pin)) {
  1518. retval = gpio_request_one(udc_info->pullup_pin,
  1519. udc_info->vbus_pin_inverted ?
  1520. GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
  1521. "udc pullup");
  1522. if (retval)
  1523. goto err_vbus_irq;
  1524. }
  1525. retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
  1526. if (retval)
  1527. goto err_add_udc;
  1528. if (s3c2410_udc_debugfs_root) {
  1529. udc->regs_info = debugfs_create_file("registers", S_IRUGO,
  1530. s3c2410_udc_debugfs_root,
  1531. udc, &s3c2410_udc_debugfs_fops);
  1532. if (!udc->regs_info)
  1533. dev_warn(dev, "debugfs file creation failed\n");
  1534. }
  1535. dev_dbg(dev, "probe ok\n");
  1536. return 0;
  1537. err_add_udc:
  1538. if (udc_info && !udc_info->udc_command &&
  1539. gpio_is_valid(udc_info->pullup_pin))
  1540. gpio_free(udc_info->pullup_pin);
  1541. err_vbus_irq:
  1542. if (udc_info && udc_info->vbus_pin > 0)
  1543. free_irq(gpio_to_irq(udc_info->vbus_pin), udc);
  1544. err_gpio_claim:
  1545. if (udc_info && udc_info->vbus_pin > 0)
  1546. gpio_free(udc_info->vbus_pin);
  1547. err_int:
  1548. free_irq(IRQ_USBD, udc);
  1549. err_map:
  1550. iounmap(base_addr);
  1551. err_mem:
  1552. release_mem_region(rsrc_start, rsrc_len);
  1553. return retval;
  1554. }
  1555. /*
  1556. * s3c2410_udc_remove
  1557. */
  1558. static int s3c2410_udc_remove(struct platform_device *pdev)
  1559. {
  1560. struct s3c2410_udc *udc = platform_get_drvdata(pdev);
  1561. unsigned int irq;
  1562. dev_dbg(&pdev->dev, "%s()\n", __func__);
  1563. if (udc->driver)
  1564. return -EBUSY;
  1565. usb_del_gadget_udc(&udc->gadget);
  1566. debugfs_remove(udc->regs_info);
  1567. if (udc_info && !udc_info->udc_command &&
  1568. gpio_is_valid(udc_info->pullup_pin))
  1569. gpio_free(udc_info->pullup_pin);
  1570. if (udc_info && udc_info->vbus_pin > 0) {
  1571. irq = gpio_to_irq(udc_info->vbus_pin);
  1572. free_irq(irq, udc);
  1573. }
  1574. free_irq(IRQ_USBD, udc);
  1575. iounmap(base_addr);
  1576. release_mem_region(rsrc_start, rsrc_len);
  1577. if (!IS_ERR(udc_clock) && udc_clock != NULL) {
  1578. clk_disable_unprepare(udc_clock);
  1579. clk_put(udc_clock);
  1580. udc_clock = NULL;
  1581. }
  1582. if (!IS_ERR(usb_bus_clock) && usb_bus_clock != NULL) {
  1583. clk_disable_unprepare(usb_bus_clock);
  1584. clk_put(usb_bus_clock);
  1585. usb_bus_clock = NULL;
  1586. }
  1587. dev_dbg(&pdev->dev, "%s: remove ok\n", __func__);
  1588. return 0;
  1589. }
  1590. #ifdef CONFIG_PM
  1591. static int
  1592. s3c2410_udc_suspend(struct platform_device *pdev, pm_message_t message)
  1593. {
  1594. s3c2410_udc_command(S3C2410_UDC_P_DISABLE);
  1595. return 0;
  1596. }
  1597. static int s3c2410_udc_resume(struct platform_device *pdev)
  1598. {
  1599. s3c2410_udc_command(S3C2410_UDC_P_ENABLE);
  1600. return 0;
  1601. }
  1602. #else
  1603. #define s3c2410_udc_suspend NULL
  1604. #define s3c2410_udc_resume NULL
  1605. #endif
  1606. static const struct platform_device_id s3c_udc_ids[] = {
  1607. { "s3c2410-usbgadget", },
  1608. { "s3c2440-usbgadget", },
  1609. { }
  1610. };
  1611. MODULE_DEVICE_TABLE(platform, s3c_udc_ids);
  1612. static struct platform_driver udc_driver_24x0 = {
  1613. .driver = {
  1614. .name = "s3c24x0-usbgadget",
  1615. },
  1616. .probe = s3c2410_udc_probe,
  1617. .remove = s3c2410_udc_remove,
  1618. .suspend = s3c2410_udc_suspend,
  1619. .resume = s3c2410_udc_resume,
  1620. .id_table = s3c_udc_ids,
  1621. };
  1622. static int __init udc_init(void)
  1623. {
  1624. int retval;
  1625. dprintk(DEBUG_NORMAL, "%s: version %s\n", gadget_name, DRIVER_VERSION);
  1626. s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name, NULL);
  1627. if (IS_ERR(s3c2410_udc_debugfs_root)) {
  1628. pr_err("%s: debugfs dir creation failed %ld\n",
  1629. gadget_name, PTR_ERR(s3c2410_udc_debugfs_root));
  1630. s3c2410_udc_debugfs_root = NULL;
  1631. }
  1632. retval = platform_driver_register(&udc_driver_24x0);
  1633. if (retval)
  1634. goto err;
  1635. return 0;
  1636. err:
  1637. debugfs_remove(s3c2410_udc_debugfs_root);
  1638. return retval;
  1639. }
  1640. static void __exit udc_exit(void)
  1641. {
  1642. platform_driver_unregister(&udc_driver_24x0);
  1643. debugfs_remove(s3c2410_udc_debugfs_root);
  1644. }
  1645. module_init(udc_init);
  1646. module_exit(udc_exit);
  1647. MODULE_AUTHOR(DRIVER_AUTHOR);
  1648. MODULE_DESCRIPTION(DRIVER_DESC);
  1649. MODULE_VERSION(DRIVER_VERSION);
  1650. MODULE_LICENSE("GPL");