i6300esb.c 12 KB

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  1. /*
  2. * i6300esb: Watchdog timer driver for Intel 6300ESB chipset
  3. *
  4. * (c) Copyright 2004 Google Inc.
  5. * (c) Copyright 2005 David Härdeman <david@2gen.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. *
  12. * based on i810-tco.c which is in turn based on softdog.c
  13. *
  14. * The timer is implemented in the following I/O controller hubs:
  15. * (See the intel documentation on http://developer.intel.com.)
  16. * 6300ESB chip : document number 300641-004
  17. *
  18. * 2004YYZZ Ross Biro
  19. * Initial version 0.01
  20. * 2004YYZZ Ross Biro
  21. * Version 0.02
  22. * 20050210 David Härdeman <david@2gen.com>
  23. * Ported driver to kernel 2.6
  24. */
  25. /*
  26. * Includes, defines, variables, module parameters, ...
  27. */
  28. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29. #include <linux/module.h>
  30. #include <linux/types.h>
  31. #include <linux/kernel.h>
  32. #include <linux/fs.h>
  33. #include <linux/mm.h>
  34. #include <linux/miscdevice.h>
  35. #include <linux/watchdog.h>
  36. #include <linux/pci.h>
  37. #include <linux/ioport.h>
  38. #include <linux/uaccess.h>
  39. #include <linux/io.h>
  40. /* Module and version information */
  41. #define ESB_VERSION "0.05"
  42. #define ESB_MODULE_NAME "i6300ESB timer"
  43. #define ESB_DRIVER_NAME ESB_MODULE_NAME ", v" ESB_VERSION
  44. /* PCI configuration registers */
  45. #define ESB_CONFIG_REG 0x60 /* Config register */
  46. #define ESB_LOCK_REG 0x68 /* WDT lock register */
  47. /* Memory mapped registers */
  48. #define ESB_TIMER1_REG (BASEADDR + 0x00)/* Timer1 value after each reset */
  49. #define ESB_TIMER2_REG (BASEADDR + 0x04)/* Timer2 value after each reset */
  50. #define ESB_GINTSR_REG (BASEADDR + 0x08)/* General Interrupt Status Register */
  51. #define ESB_RELOAD_REG (BASEADDR + 0x0c)/* Reload register */
  52. /* Lock register bits */
  53. #define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
  54. #define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
  55. #define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
  56. /* Config register bits */
  57. #define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
  58. #define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
  59. #define ESB_WDT_INTTYPE (0x03 << 0) /* Interrupt type on timer1 timeout */
  60. /* Reload register bits */
  61. #define ESB_WDT_TIMEOUT (0x01 << 9) /* Watchdog timed out */
  62. #define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
  63. /* Magic constants */
  64. #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
  65. #define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
  66. /* internal variables */
  67. static void __iomem *BASEADDR;
  68. static DEFINE_SPINLOCK(esb_lock); /* Guards the hardware */
  69. static unsigned long timer_alive;
  70. static struct pci_dev *esb_pci;
  71. static unsigned short triggered; /* The status of the watchdog upon boot */
  72. static char esb_expect_close;
  73. /* We can only use 1 card due to the /dev/watchdog restriction */
  74. static int cards_found;
  75. /* module parameters */
  76. /* 30 sec default heartbeat (1 < heartbeat < 2*1023) */
  77. #define WATCHDOG_HEARTBEAT 30
  78. static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
  79. module_param(heartbeat, int, 0);
  80. MODULE_PARM_DESC(heartbeat,
  81. "Watchdog heartbeat in seconds. (1<heartbeat<2046, default="
  82. __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
  83. static bool nowayout = WATCHDOG_NOWAYOUT;
  84. module_param(nowayout, bool, 0);
  85. MODULE_PARM_DESC(nowayout,
  86. "Watchdog cannot be stopped once started (default="
  87. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  88. /*
  89. * Some i6300ESB specific functions
  90. */
  91. /*
  92. * Prepare for reloading the timer by unlocking the proper registers.
  93. * This is performed by first writing 0x80 followed by 0x86 to the
  94. * reload register. After this the appropriate registers can be written
  95. * to once before they need to be unlocked again.
  96. */
  97. static inline void esb_unlock_registers(void)
  98. {
  99. writew(ESB_UNLOCK1, ESB_RELOAD_REG);
  100. writew(ESB_UNLOCK2, ESB_RELOAD_REG);
  101. }
  102. static int esb_timer_start(void)
  103. {
  104. u8 val;
  105. spin_lock(&esb_lock);
  106. esb_unlock_registers();
  107. writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
  108. /* Enable or Enable + Lock? */
  109. val = ESB_WDT_ENABLE | (nowayout ? ESB_WDT_LOCK : 0x00);
  110. pci_write_config_byte(esb_pci, ESB_LOCK_REG, val);
  111. spin_unlock(&esb_lock);
  112. return 0;
  113. }
  114. static int esb_timer_stop(void)
  115. {
  116. u8 val;
  117. spin_lock(&esb_lock);
  118. /* First, reset timers as suggested by the docs */
  119. esb_unlock_registers();
  120. writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
  121. /* Then disable the WDT */
  122. pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x0);
  123. pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val);
  124. spin_unlock(&esb_lock);
  125. /* Returns 0 if the timer was disabled, non-zero otherwise */
  126. return val & ESB_WDT_ENABLE;
  127. }
  128. static void esb_timer_keepalive(void)
  129. {
  130. spin_lock(&esb_lock);
  131. esb_unlock_registers();
  132. writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
  133. /* FIXME: Do we need to flush anything here? */
  134. spin_unlock(&esb_lock);
  135. }
  136. static int esb_timer_set_heartbeat(int time)
  137. {
  138. u32 val;
  139. if (time < 0x1 || time > (2 * 0x03ff))
  140. return -EINVAL;
  141. spin_lock(&esb_lock);
  142. /* We shift by 9, so if we are passed a value of 1 sec,
  143. * val will be 1 << 9 = 512, then write that to two
  144. * timers => 2 * 512 = 1024 (which is decremented at 1KHz)
  145. */
  146. val = time << 9;
  147. /* Write timer 1 */
  148. esb_unlock_registers();
  149. writel(val, ESB_TIMER1_REG);
  150. /* Write timer 2 */
  151. esb_unlock_registers();
  152. writel(val, ESB_TIMER2_REG);
  153. /* Reload */
  154. esb_unlock_registers();
  155. writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
  156. /* FIXME: Do we need to flush everything out? */
  157. /* Done */
  158. heartbeat = time;
  159. spin_unlock(&esb_lock);
  160. return 0;
  161. }
  162. /*
  163. * /dev/watchdog handling
  164. */
  165. static int esb_open(struct inode *inode, struct file *file)
  166. {
  167. /* /dev/watchdog can only be opened once */
  168. if (test_and_set_bit(0, &timer_alive))
  169. return -EBUSY;
  170. /* Reload and activate timer */
  171. esb_timer_start();
  172. return nonseekable_open(inode, file);
  173. }
  174. static int esb_release(struct inode *inode, struct file *file)
  175. {
  176. /* Shut off the timer. */
  177. if (esb_expect_close == 42)
  178. esb_timer_stop();
  179. else {
  180. pr_crit("Unexpected close, not stopping watchdog!\n");
  181. esb_timer_keepalive();
  182. }
  183. clear_bit(0, &timer_alive);
  184. esb_expect_close = 0;
  185. return 0;
  186. }
  187. static ssize_t esb_write(struct file *file, const char __user *data,
  188. size_t len, loff_t *ppos)
  189. {
  190. /* See if we got the magic character 'V' and reload the timer */
  191. if (len) {
  192. if (!nowayout) {
  193. size_t i;
  194. /* note: just in case someone wrote the magic character
  195. * five months ago... */
  196. esb_expect_close = 0;
  197. /* scan to see whether or not we got the
  198. * magic character */
  199. for (i = 0; i != len; i++) {
  200. char c;
  201. if (get_user(c, data + i))
  202. return -EFAULT;
  203. if (c == 'V')
  204. esb_expect_close = 42;
  205. }
  206. }
  207. /* someone wrote to us, we should reload the timer */
  208. esb_timer_keepalive();
  209. }
  210. return len;
  211. }
  212. static long esb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  213. {
  214. int new_options, retval = -EINVAL;
  215. int new_heartbeat;
  216. void __user *argp = (void __user *)arg;
  217. int __user *p = argp;
  218. static const struct watchdog_info ident = {
  219. .options = WDIOF_SETTIMEOUT |
  220. WDIOF_KEEPALIVEPING |
  221. WDIOF_MAGICCLOSE,
  222. .firmware_version = 0,
  223. .identity = ESB_MODULE_NAME,
  224. };
  225. switch (cmd) {
  226. case WDIOC_GETSUPPORT:
  227. return copy_to_user(argp, &ident,
  228. sizeof(ident)) ? -EFAULT : 0;
  229. case WDIOC_GETSTATUS:
  230. return put_user(0, p);
  231. case WDIOC_GETBOOTSTATUS:
  232. return put_user(triggered, p);
  233. case WDIOC_SETOPTIONS:
  234. {
  235. if (get_user(new_options, p))
  236. return -EFAULT;
  237. if (new_options & WDIOS_DISABLECARD) {
  238. esb_timer_stop();
  239. retval = 0;
  240. }
  241. if (new_options & WDIOS_ENABLECARD) {
  242. esb_timer_start();
  243. retval = 0;
  244. }
  245. return retval;
  246. }
  247. case WDIOC_KEEPALIVE:
  248. esb_timer_keepalive();
  249. return 0;
  250. case WDIOC_SETTIMEOUT:
  251. {
  252. if (get_user(new_heartbeat, p))
  253. return -EFAULT;
  254. if (esb_timer_set_heartbeat(new_heartbeat))
  255. return -EINVAL;
  256. esb_timer_keepalive();
  257. /* Fall */
  258. }
  259. case WDIOC_GETTIMEOUT:
  260. return put_user(heartbeat, p);
  261. default:
  262. return -ENOTTY;
  263. }
  264. }
  265. /*
  266. * Kernel Interfaces
  267. */
  268. static const struct file_operations esb_fops = {
  269. .owner = THIS_MODULE,
  270. .llseek = no_llseek,
  271. .write = esb_write,
  272. .unlocked_ioctl = esb_ioctl,
  273. .open = esb_open,
  274. .release = esb_release,
  275. };
  276. static struct miscdevice esb_miscdev = {
  277. .minor = WATCHDOG_MINOR,
  278. .name = "watchdog",
  279. .fops = &esb_fops,
  280. };
  281. /*
  282. * Data for PCI driver interface
  283. */
  284. static const struct pci_device_id esb_pci_tbl[] = {
  285. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), },
  286. { 0, }, /* End of list */
  287. };
  288. MODULE_DEVICE_TABLE(pci, esb_pci_tbl);
  289. /*
  290. * Init & exit routines
  291. */
  292. static unsigned char esb_getdevice(struct pci_dev *pdev)
  293. {
  294. if (pci_enable_device(pdev)) {
  295. pr_err("failed to enable device\n");
  296. goto err_devput;
  297. }
  298. if (pci_request_region(pdev, 0, ESB_MODULE_NAME)) {
  299. pr_err("failed to request region\n");
  300. goto err_disable;
  301. }
  302. BASEADDR = pci_ioremap_bar(pdev, 0);
  303. if (BASEADDR == NULL) {
  304. /* Something's wrong here, BASEADDR has to be set */
  305. pr_err("failed to get BASEADDR\n");
  306. goto err_release;
  307. }
  308. /* Done */
  309. esb_pci = pdev;
  310. return 1;
  311. err_release:
  312. pci_release_region(pdev, 0);
  313. err_disable:
  314. pci_disable_device(pdev);
  315. err_devput:
  316. return 0;
  317. }
  318. static void esb_initdevice(void)
  319. {
  320. u8 val1;
  321. u16 val2;
  322. /*
  323. * Config register:
  324. * Bit 5 : 0 = Enable WDT_OUTPUT
  325. * Bit 2 : 0 = set the timer frequency to the PCI clock
  326. * divided by 2^15 (approx 1KHz).
  327. * Bits 1:0 : 11 = WDT_INT_TYPE Disabled.
  328. * The watchdog has two timers, it can be setup so that the
  329. * expiry of timer1 results in an interrupt and the expiry of
  330. * timer2 results in a reboot. We set it to not generate
  331. * any interrupts as there is not much we can do with it
  332. * right now.
  333. */
  334. pci_write_config_word(esb_pci, ESB_CONFIG_REG, 0x0003);
  335. /* Check that the WDT isn't already locked */
  336. pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val1);
  337. if (val1 & ESB_WDT_LOCK)
  338. pr_warn("nowayout already set\n");
  339. /* Set the timer to watchdog mode and disable it for now */
  340. pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x00);
  341. /* Check if the watchdog was previously triggered */
  342. esb_unlock_registers();
  343. val2 = readw(ESB_RELOAD_REG);
  344. if (val2 & ESB_WDT_TIMEOUT)
  345. triggered = WDIOF_CARDRESET;
  346. /* Reset WDT_TIMEOUT flag and timers */
  347. esb_unlock_registers();
  348. writew((ESB_WDT_TIMEOUT | ESB_WDT_RELOAD), ESB_RELOAD_REG);
  349. /* And set the correct timeout value */
  350. esb_timer_set_heartbeat(heartbeat);
  351. }
  352. static int esb_probe(struct pci_dev *pdev,
  353. const struct pci_device_id *ent)
  354. {
  355. int ret;
  356. cards_found++;
  357. if (cards_found == 1)
  358. pr_info("Intel 6300ESB WatchDog Timer Driver v%s\n",
  359. ESB_VERSION);
  360. if (cards_found > 1) {
  361. pr_err("This driver only supports 1 device\n");
  362. return -ENODEV;
  363. }
  364. /* Check whether or not the hardware watchdog is there */
  365. if (!esb_getdevice(pdev) || esb_pci == NULL)
  366. return -ENODEV;
  367. /* Check that the heartbeat value is within it's range;
  368. if not reset to the default */
  369. if (heartbeat < 0x1 || heartbeat > 2 * 0x03ff) {
  370. heartbeat = WATCHDOG_HEARTBEAT;
  371. pr_info("heartbeat value must be 1<heartbeat<2046, using %d\n",
  372. heartbeat);
  373. }
  374. /* Initialize the watchdog and make sure it does not run */
  375. esb_initdevice();
  376. /* Register the watchdog so that userspace has access to it */
  377. ret = misc_register(&esb_miscdev);
  378. if (ret != 0) {
  379. pr_err("cannot register miscdev on minor=%d (err=%d)\n",
  380. WATCHDOG_MINOR, ret);
  381. goto err_unmap;
  382. }
  383. pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n",
  384. BASEADDR, heartbeat, nowayout);
  385. return 0;
  386. err_unmap:
  387. iounmap(BASEADDR);
  388. pci_release_region(esb_pci, 0);
  389. pci_disable_device(esb_pci);
  390. esb_pci = NULL;
  391. return ret;
  392. }
  393. static void esb_remove(struct pci_dev *pdev)
  394. {
  395. /* Stop the timer before we leave */
  396. if (!nowayout)
  397. esb_timer_stop();
  398. /* Deregister */
  399. misc_deregister(&esb_miscdev);
  400. iounmap(BASEADDR);
  401. pci_release_region(esb_pci, 0);
  402. pci_disable_device(esb_pci);
  403. esb_pci = NULL;
  404. }
  405. static void esb_shutdown(struct pci_dev *pdev)
  406. {
  407. esb_timer_stop();
  408. }
  409. static struct pci_driver esb_driver = {
  410. .name = ESB_MODULE_NAME,
  411. .id_table = esb_pci_tbl,
  412. .probe = esb_probe,
  413. .remove = esb_remove,
  414. .shutdown = esb_shutdown,
  415. };
  416. module_pci_driver(esb_driver);
  417. MODULE_AUTHOR("Ross Biro and David Härdeman");
  418. MODULE_DESCRIPTION("Watchdog driver for Intel 6300ESB chipsets");
  419. MODULE_LICENSE("GPL");