jz4740_wdt.c 6.3 KB

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  1. /*
  2. * Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
  3. * JZ4740 Watchdog driver
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2 of the License, or (at your
  8. * option) any later version.
  9. *
  10. * You should have received a copy of the GNU General Public License along
  11. * with this program; if not, write to the Free Software Foundation, Inc.,
  12. * 675 Mass Ave, Cambridge, MA 02139, USA.
  13. *
  14. */
  15. #include <linux/module.h>
  16. #include <linux/moduleparam.h>
  17. #include <linux/types.h>
  18. #include <linux/kernel.h>
  19. #include <linux/watchdog.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/io.h>
  22. #include <linux/device.h>
  23. #include <linux/clk.h>
  24. #include <linux/slab.h>
  25. #include <linux/err.h>
  26. #include <linux/of.h>
  27. #include <asm/mach-jz4740/timer.h>
  28. #define JZ_REG_WDT_TIMER_DATA 0x0
  29. #define JZ_REG_WDT_COUNTER_ENABLE 0x4
  30. #define JZ_REG_WDT_TIMER_COUNTER 0x8
  31. #define JZ_REG_WDT_TIMER_CONTROL 0xC
  32. #define JZ_WDT_CLOCK_PCLK 0x1
  33. #define JZ_WDT_CLOCK_RTC 0x2
  34. #define JZ_WDT_CLOCK_EXT 0x4
  35. #define JZ_WDT_CLOCK_DIV_SHIFT 3
  36. #define JZ_WDT_CLOCK_DIV_1 (0 << JZ_WDT_CLOCK_DIV_SHIFT)
  37. #define JZ_WDT_CLOCK_DIV_4 (1 << JZ_WDT_CLOCK_DIV_SHIFT)
  38. #define JZ_WDT_CLOCK_DIV_16 (2 << JZ_WDT_CLOCK_DIV_SHIFT)
  39. #define JZ_WDT_CLOCK_DIV_64 (3 << JZ_WDT_CLOCK_DIV_SHIFT)
  40. #define JZ_WDT_CLOCK_DIV_256 (4 << JZ_WDT_CLOCK_DIV_SHIFT)
  41. #define JZ_WDT_CLOCK_DIV_1024 (5 << JZ_WDT_CLOCK_DIV_SHIFT)
  42. #define DEFAULT_HEARTBEAT 5
  43. #define MAX_HEARTBEAT 2048
  44. static bool nowayout = WATCHDOG_NOWAYOUT;
  45. module_param(nowayout, bool, 0);
  46. MODULE_PARM_DESC(nowayout,
  47. "Watchdog cannot be stopped once started (default="
  48. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  49. static unsigned int heartbeat = DEFAULT_HEARTBEAT;
  50. module_param(heartbeat, uint, 0);
  51. MODULE_PARM_DESC(heartbeat,
  52. "Watchdog heartbeat period in seconds from 1 to "
  53. __MODULE_STRING(MAX_HEARTBEAT) ", default "
  54. __MODULE_STRING(DEFAULT_HEARTBEAT));
  55. struct jz4740_wdt_drvdata {
  56. struct watchdog_device wdt;
  57. void __iomem *base;
  58. struct clk *rtc_clk;
  59. };
  60. static int jz4740_wdt_ping(struct watchdog_device *wdt_dev)
  61. {
  62. struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
  63. writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
  64. return 0;
  65. }
  66. static int jz4740_wdt_set_timeout(struct watchdog_device *wdt_dev,
  67. unsigned int new_timeout)
  68. {
  69. struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
  70. unsigned int rtc_clk_rate;
  71. unsigned int timeout_value;
  72. unsigned short clock_div = JZ_WDT_CLOCK_DIV_1;
  73. rtc_clk_rate = clk_get_rate(drvdata->rtc_clk);
  74. timeout_value = rtc_clk_rate * new_timeout;
  75. while (timeout_value > 0xffff) {
  76. if (clock_div == JZ_WDT_CLOCK_DIV_1024) {
  77. /* Requested timeout too high;
  78. * use highest possible value. */
  79. timeout_value = 0xffff;
  80. break;
  81. }
  82. timeout_value >>= 2;
  83. clock_div += (1 << JZ_WDT_CLOCK_DIV_SHIFT);
  84. }
  85. writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
  86. writew(clock_div, drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
  87. writew((u16)timeout_value, drvdata->base + JZ_REG_WDT_TIMER_DATA);
  88. writew(0x0, drvdata->base + JZ_REG_WDT_TIMER_COUNTER);
  89. writew(clock_div | JZ_WDT_CLOCK_RTC,
  90. drvdata->base + JZ_REG_WDT_TIMER_CONTROL);
  91. writeb(0x1, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
  92. wdt_dev->timeout = new_timeout;
  93. return 0;
  94. }
  95. static int jz4740_wdt_start(struct watchdog_device *wdt_dev)
  96. {
  97. jz4740_timer_enable_watchdog();
  98. jz4740_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
  99. return 0;
  100. }
  101. static int jz4740_wdt_stop(struct watchdog_device *wdt_dev)
  102. {
  103. struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
  104. jz4740_timer_disable_watchdog();
  105. writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
  106. return 0;
  107. }
  108. static const struct watchdog_info jz4740_wdt_info = {
  109. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
  110. .identity = "jz4740 Watchdog",
  111. };
  112. static const struct watchdog_ops jz4740_wdt_ops = {
  113. .owner = THIS_MODULE,
  114. .start = jz4740_wdt_start,
  115. .stop = jz4740_wdt_stop,
  116. .ping = jz4740_wdt_ping,
  117. .set_timeout = jz4740_wdt_set_timeout,
  118. };
  119. #ifdef CONFIG_OF
  120. static const struct of_device_id jz4740_wdt_of_matches[] = {
  121. { .compatible = "ingenic,jz4740-watchdog", },
  122. { /* sentinel */ }
  123. };
  124. MODULE_DEVICE_TABLE(of, jz4740_wdt_of_matches)
  125. #endif
  126. static int jz4740_wdt_probe(struct platform_device *pdev)
  127. {
  128. struct jz4740_wdt_drvdata *drvdata;
  129. struct watchdog_device *jz4740_wdt;
  130. struct resource *res;
  131. int ret;
  132. drvdata = devm_kzalloc(&pdev->dev, sizeof(struct jz4740_wdt_drvdata),
  133. GFP_KERNEL);
  134. if (!drvdata) {
  135. dev_err(&pdev->dev, "Unable to alloacate watchdog device\n");
  136. return -ENOMEM;
  137. }
  138. if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
  139. heartbeat = DEFAULT_HEARTBEAT;
  140. jz4740_wdt = &drvdata->wdt;
  141. jz4740_wdt->info = &jz4740_wdt_info;
  142. jz4740_wdt->ops = &jz4740_wdt_ops;
  143. jz4740_wdt->timeout = heartbeat;
  144. jz4740_wdt->min_timeout = 1;
  145. jz4740_wdt->max_timeout = MAX_HEARTBEAT;
  146. jz4740_wdt->parent = &pdev->dev;
  147. watchdog_set_nowayout(jz4740_wdt, nowayout);
  148. watchdog_set_drvdata(jz4740_wdt, drvdata);
  149. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  150. drvdata->base = devm_ioremap_resource(&pdev->dev, res);
  151. if (IS_ERR(drvdata->base)) {
  152. ret = PTR_ERR(drvdata->base);
  153. goto err_out;
  154. }
  155. drvdata->rtc_clk = clk_get(&pdev->dev, "rtc");
  156. if (IS_ERR(drvdata->rtc_clk)) {
  157. dev_err(&pdev->dev, "cannot find RTC clock\n");
  158. ret = PTR_ERR(drvdata->rtc_clk);
  159. goto err_out;
  160. }
  161. ret = watchdog_register_device(&drvdata->wdt);
  162. if (ret < 0)
  163. goto err_disable_clk;
  164. platform_set_drvdata(pdev, drvdata);
  165. return 0;
  166. err_disable_clk:
  167. clk_put(drvdata->rtc_clk);
  168. err_out:
  169. return ret;
  170. }
  171. static int jz4740_wdt_remove(struct platform_device *pdev)
  172. {
  173. struct jz4740_wdt_drvdata *drvdata = platform_get_drvdata(pdev);
  174. jz4740_wdt_stop(&drvdata->wdt);
  175. watchdog_unregister_device(&drvdata->wdt);
  176. clk_put(drvdata->rtc_clk);
  177. return 0;
  178. }
  179. static struct platform_driver jz4740_wdt_driver = {
  180. .probe = jz4740_wdt_probe,
  181. .remove = jz4740_wdt_remove,
  182. .driver = {
  183. .name = "jz4740-wdt",
  184. .of_match_table = of_match_ptr(jz4740_wdt_of_matches),
  185. },
  186. };
  187. module_platform_driver(jz4740_wdt_driver);
  188. MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
  189. MODULE_DESCRIPTION("jz4740 Watchdog Driver");
  190. MODULE_LICENSE("GPL");
  191. MODULE_ALIAS("platform:jz4740-wdt");