orion_wdt.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655
  1. /*
  2. * drivers/watchdog/orion_wdt.c
  3. *
  4. * Watchdog driver for Orion/Kirkwood processors
  5. *
  6. * Author: Sylver Bruneau <sylver.bruneau@googlemail.com>
  7. *
  8. * This file is licensed under the terms of the GNU General Public
  9. * License version 2. This program is licensed "as is" without any
  10. * warranty of any kind, whether express or implied.
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/types.h>
  16. #include <linux/kernel.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/watchdog.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/io.h>
  21. #include <linux/clk.h>
  22. #include <linux/err.h>
  23. #include <linux/of.h>
  24. #include <linux/of_device.h>
  25. /* RSTOUT mask register physical address for Orion5x, Kirkwood and Dove */
  26. #define ORION_RSTOUT_MASK_OFFSET 0x20108
  27. /* Internal registers can be configured at any 1 MiB aligned address */
  28. #define INTERNAL_REGS_MASK ~(SZ_1M - 1)
  29. /*
  30. * Watchdog timer block registers.
  31. */
  32. #define TIMER_CTRL 0x0000
  33. #define TIMER_A370_STATUS 0x04
  34. #define WDT_MAX_CYCLE_COUNT 0xffffffff
  35. #define WDT_A370_RATIO_MASK(v) ((v) << 16)
  36. #define WDT_A370_RATIO_SHIFT 5
  37. #define WDT_A370_RATIO (1 << WDT_A370_RATIO_SHIFT)
  38. #define WDT_AXP_FIXED_ENABLE_BIT BIT(10)
  39. #define WDT_A370_EXPIRED BIT(31)
  40. static bool nowayout = WATCHDOG_NOWAYOUT;
  41. static int heartbeat = -1; /* module parameter (seconds) */
  42. struct orion_watchdog;
  43. struct orion_watchdog_data {
  44. int wdt_counter_offset;
  45. int wdt_enable_bit;
  46. int rstout_enable_bit;
  47. int rstout_mask_bit;
  48. int (*clock_init)(struct platform_device *,
  49. struct orion_watchdog *);
  50. int (*enabled)(struct orion_watchdog *);
  51. int (*start)(struct watchdog_device *);
  52. int (*stop)(struct watchdog_device *);
  53. };
  54. struct orion_watchdog {
  55. struct watchdog_device wdt;
  56. void __iomem *reg;
  57. void __iomem *rstout;
  58. void __iomem *rstout_mask;
  59. unsigned long clk_rate;
  60. struct clk *clk;
  61. const struct orion_watchdog_data *data;
  62. };
  63. static int orion_wdt_clock_init(struct platform_device *pdev,
  64. struct orion_watchdog *dev)
  65. {
  66. int ret;
  67. dev->clk = clk_get(&pdev->dev, NULL);
  68. if (IS_ERR(dev->clk))
  69. return PTR_ERR(dev->clk);
  70. ret = clk_prepare_enable(dev->clk);
  71. if (ret) {
  72. clk_put(dev->clk);
  73. return ret;
  74. }
  75. dev->clk_rate = clk_get_rate(dev->clk);
  76. return 0;
  77. }
  78. static int armada370_wdt_clock_init(struct platform_device *pdev,
  79. struct orion_watchdog *dev)
  80. {
  81. int ret;
  82. dev->clk = clk_get(&pdev->dev, NULL);
  83. if (IS_ERR(dev->clk))
  84. return PTR_ERR(dev->clk);
  85. ret = clk_prepare_enable(dev->clk);
  86. if (ret) {
  87. clk_put(dev->clk);
  88. return ret;
  89. }
  90. /* Setup watchdog input clock */
  91. atomic_io_modify(dev->reg + TIMER_CTRL,
  92. WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT),
  93. WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT));
  94. dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO;
  95. return 0;
  96. }
  97. static int armada375_wdt_clock_init(struct platform_device *pdev,
  98. struct orion_watchdog *dev)
  99. {
  100. int ret;
  101. dev->clk = of_clk_get_by_name(pdev->dev.of_node, "fixed");
  102. if (!IS_ERR(dev->clk)) {
  103. ret = clk_prepare_enable(dev->clk);
  104. if (ret) {
  105. clk_put(dev->clk);
  106. return ret;
  107. }
  108. atomic_io_modify(dev->reg + TIMER_CTRL,
  109. WDT_AXP_FIXED_ENABLE_BIT,
  110. WDT_AXP_FIXED_ENABLE_BIT);
  111. dev->clk_rate = clk_get_rate(dev->clk);
  112. return 0;
  113. }
  114. /* Mandatory fallback for proper devicetree backward compatibility */
  115. dev->clk = clk_get(&pdev->dev, NULL);
  116. if (IS_ERR(dev->clk))
  117. return PTR_ERR(dev->clk);
  118. ret = clk_prepare_enable(dev->clk);
  119. if (ret) {
  120. clk_put(dev->clk);
  121. return ret;
  122. }
  123. atomic_io_modify(dev->reg + TIMER_CTRL,
  124. WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT),
  125. WDT_A370_RATIO_MASK(WDT_A370_RATIO_SHIFT));
  126. dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO;
  127. return 0;
  128. }
  129. static int armadaxp_wdt_clock_init(struct platform_device *pdev,
  130. struct orion_watchdog *dev)
  131. {
  132. int ret;
  133. dev->clk = of_clk_get_by_name(pdev->dev.of_node, "fixed");
  134. if (IS_ERR(dev->clk))
  135. return PTR_ERR(dev->clk);
  136. ret = clk_prepare_enable(dev->clk);
  137. if (ret) {
  138. clk_put(dev->clk);
  139. return ret;
  140. }
  141. /* Enable the fixed watchdog clock input */
  142. atomic_io_modify(dev->reg + TIMER_CTRL,
  143. WDT_AXP_FIXED_ENABLE_BIT,
  144. WDT_AXP_FIXED_ENABLE_BIT);
  145. dev->clk_rate = clk_get_rate(dev->clk);
  146. return 0;
  147. }
  148. static int orion_wdt_ping(struct watchdog_device *wdt_dev)
  149. {
  150. struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
  151. /* Reload watchdog duration */
  152. writel(dev->clk_rate * wdt_dev->timeout,
  153. dev->reg + dev->data->wdt_counter_offset);
  154. return 0;
  155. }
  156. static int armada375_start(struct watchdog_device *wdt_dev)
  157. {
  158. struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
  159. u32 reg;
  160. /* Set watchdog duration */
  161. writel(dev->clk_rate * wdt_dev->timeout,
  162. dev->reg + dev->data->wdt_counter_offset);
  163. /* Clear the watchdog expiration bit */
  164. atomic_io_modify(dev->reg + TIMER_A370_STATUS, WDT_A370_EXPIRED, 0);
  165. /* Enable watchdog timer */
  166. atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit,
  167. dev->data->wdt_enable_bit);
  168. /* Enable reset on watchdog */
  169. reg = readl(dev->rstout);
  170. reg |= dev->data->rstout_enable_bit;
  171. writel(reg, dev->rstout);
  172. atomic_io_modify(dev->rstout_mask, dev->data->rstout_mask_bit, 0);
  173. return 0;
  174. }
  175. static int armada370_start(struct watchdog_device *wdt_dev)
  176. {
  177. struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
  178. u32 reg;
  179. /* Set watchdog duration */
  180. writel(dev->clk_rate * wdt_dev->timeout,
  181. dev->reg + dev->data->wdt_counter_offset);
  182. /* Clear the watchdog expiration bit */
  183. atomic_io_modify(dev->reg + TIMER_A370_STATUS, WDT_A370_EXPIRED, 0);
  184. /* Enable watchdog timer */
  185. atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit,
  186. dev->data->wdt_enable_bit);
  187. /* Enable reset on watchdog */
  188. reg = readl(dev->rstout);
  189. reg |= dev->data->rstout_enable_bit;
  190. writel(reg, dev->rstout);
  191. return 0;
  192. }
  193. static int orion_start(struct watchdog_device *wdt_dev)
  194. {
  195. struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
  196. /* Set watchdog duration */
  197. writel(dev->clk_rate * wdt_dev->timeout,
  198. dev->reg + dev->data->wdt_counter_offset);
  199. /* Enable watchdog timer */
  200. atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit,
  201. dev->data->wdt_enable_bit);
  202. /* Enable reset on watchdog */
  203. atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit,
  204. dev->data->rstout_enable_bit);
  205. return 0;
  206. }
  207. static int orion_wdt_start(struct watchdog_device *wdt_dev)
  208. {
  209. struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
  210. /* There are some per-SoC quirks to handle */
  211. return dev->data->start(wdt_dev);
  212. }
  213. static int orion_stop(struct watchdog_device *wdt_dev)
  214. {
  215. struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
  216. /* Disable reset on watchdog */
  217. atomic_io_modify(dev->rstout, dev->data->rstout_enable_bit, 0);
  218. /* Disable watchdog timer */
  219. atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0);
  220. return 0;
  221. }
  222. static int armada375_stop(struct watchdog_device *wdt_dev)
  223. {
  224. struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
  225. u32 reg;
  226. /* Disable reset on watchdog */
  227. atomic_io_modify(dev->rstout_mask, dev->data->rstout_mask_bit,
  228. dev->data->rstout_mask_bit);
  229. reg = readl(dev->rstout);
  230. reg &= ~dev->data->rstout_enable_bit;
  231. writel(reg, dev->rstout);
  232. /* Disable watchdog timer */
  233. atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0);
  234. return 0;
  235. }
  236. static int armada370_stop(struct watchdog_device *wdt_dev)
  237. {
  238. struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
  239. u32 reg;
  240. /* Disable reset on watchdog */
  241. reg = readl(dev->rstout);
  242. reg &= ~dev->data->rstout_enable_bit;
  243. writel(reg, dev->rstout);
  244. /* Disable watchdog timer */
  245. atomic_io_modify(dev->reg + TIMER_CTRL, dev->data->wdt_enable_bit, 0);
  246. return 0;
  247. }
  248. static int orion_wdt_stop(struct watchdog_device *wdt_dev)
  249. {
  250. struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
  251. return dev->data->stop(wdt_dev);
  252. }
  253. static int orion_enabled(struct orion_watchdog *dev)
  254. {
  255. bool enabled, running;
  256. enabled = readl(dev->rstout) & dev->data->rstout_enable_bit;
  257. running = readl(dev->reg + TIMER_CTRL) & dev->data->wdt_enable_bit;
  258. return enabled && running;
  259. }
  260. static int armada375_enabled(struct orion_watchdog *dev)
  261. {
  262. bool masked, enabled, running;
  263. masked = readl(dev->rstout_mask) & dev->data->rstout_mask_bit;
  264. enabled = readl(dev->rstout) & dev->data->rstout_enable_bit;
  265. running = readl(dev->reg + TIMER_CTRL) & dev->data->wdt_enable_bit;
  266. return !masked && enabled && running;
  267. }
  268. static int orion_wdt_enabled(struct watchdog_device *wdt_dev)
  269. {
  270. struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
  271. return dev->data->enabled(dev);
  272. }
  273. static unsigned int orion_wdt_get_timeleft(struct watchdog_device *wdt_dev)
  274. {
  275. struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
  276. return readl(dev->reg + dev->data->wdt_counter_offset) / dev->clk_rate;
  277. }
  278. static int orion_wdt_set_timeout(struct watchdog_device *wdt_dev,
  279. unsigned int timeout)
  280. {
  281. wdt_dev->timeout = timeout;
  282. return 0;
  283. }
  284. static const struct watchdog_info orion_wdt_info = {
  285. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
  286. .identity = "Orion Watchdog",
  287. };
  288. static const struct watchdog_ops orion_wdt_ops = {
  289. .owner = THIS_MODULE,
  290. .start = orion_wdt_start,
  291. .stop = orion_wdt_stop,
  292. .ping = orion_wdt_ping,
  293. .set_timeout = orion_wdt_set_timeout,
  294. .get_timeleft = orion_wdt_get_timeleft,
  295. };
  296. static irqreturn_t orion_wdt_irq(int irq, void *devid)
  297. {
  298. panic("Watchdog Timeout");
  299. return IRQ_HANDLED;
  300. }
  301. /*
  302. * The original devicetree binding for this driver specified only
  303. * one memory resource, so in order to keep DT backwards compatibility
  304. * we try to fallback to a hardcoded register address, if the resource
  305. * is missing from the devicetree.
  306. */
  307. static void __iomem *orion_wdt_ioremap_rstout(struct platform_device *pdev,
  308. phys_addr_t internal_regs)
  309. {
  310. struct resource *res;
  311. phys_addr_t rstout;
  312. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  313. if (res)
  314. return devm_ioremap(&pdev->dev, res->start,
  315. resource_size(res));
  316. rstout = internal_regs + ORION_RSTOUT_MASK_OFFSET;
  317. WARN(1, FW_BUG "falling back to harcoded RSTOUT reg %pa\n", &rstout);
  318. return devm_ioremap(&pdev->dev, rstout, 0x4);
  319. }
  320. static const struct orion_watchdog_data orion_data = {
  321. .rstout_enable_bit = BIT(1),
  322. .wdt_enable_bit = BIT(4),
  323. .wdt_counter_offset = 0x24,
  324. .clock_init = orion_wdt_clock_init,
  325. .enabled = orion_enabled,
  326. .start = orion_start,
  327. .stop = orion_stop,
  328. };
  329. static const struct orion_watchdog_data armada370_data = {
  330. .rstout_enable_bit = BIT(8),
  331. .wdt_enable_bit = BIT(8),
  332. .wdt_counter_offset = 0x34,
  333. .clock_init = armada370_wdt_clock_init,
  334. .enabled = orion_enabled,
  335. .start = armada370_start,
  336. .stop = armada370_stop,
  337. };
  338. static const struct orion_watchdog_data armadaxp_data = {
  339. .rstout_enable_bit = BIT(8),
  340. .wdt_enable_bit = BIT(8),
  341. .wdt_counter_offset = 0x34,
  342. .clock_init = armadaxp_wdt_clock_init,
  343. .enabled = orion_enabled,
  344. .start = armada370_start,
  345. .stop = armada370_stop,
  346. };
  347. static const struct orion_watchdog_data armada375_data = {
  348. .rstout_enable_bit = BIT(8),
  349. .rstout_mask_bit = BIT(10),
  350. .wdt_enable_bit = BIT(8),
  351. .wdt_counter_offset = 0x34,
  352. .clock_init = armada375_wdt_clock_init,
  353. .enabled = armada375_enabled,
  354. .start = armada375_start,
  355. .stop = armada375_stop,
  356. };
  357. static const struct orion_watchdog_data armada380_data = {
  358. .rstout_enable_bit = BIT(8),
  359. .rstout_mask_bit = BIT(10),
  360. .wdt_enable_bit = BIT(8),
  361. .wdt_counter_offset = 0x34,
  362. .clock_init = armadaxp_wdt_clock_init,
  363. .enabled = armada375_enabled,
  364. .start = armada375_start,
  365. .stop = armada375_stop,
  366. };
  367. static const struct of_device_id orion_wdt_of_match_table[] = {
  368. {
  369. .compatible = "marvell,orion-wdt",
  370. .data = &orion_data,
  371. },
  372. {
  373. .compatible = "marvell,armada-370-wdt",
  374. .data = &armada370_data,
  375. },
  376. {
  377. .compatible = "marvell,armada-xp-wdt",
  378. .data = &armadaxp_data,
  379. },
  380. {
  381. .compatible = "marvell,armada-375-wdt",
  382. .data = &armada375_data,
  383. },
  384. {
  385. .compatible = "marvell,armada-380-wdt",
  386. .data = &armada380_data,
  387. },
  388. {},
  389. };
  390. MODULE_DEVICE_TABLE(of, orion_wdt_of_match_table);
  391. static int orion_wdt_get_regs(struct platform_device *pdev,
  392. struct orion_watchdog *dev)
  393. {
  394. struct device_node *node = pdev->dev.of_node;
  395. struct resource *res;
  396. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  397. if (!res)
  398. return -ENODEV;
  399. dev->reg = devm_ioremap(&pdev->dev, res->start,
  400. resource_size(res));
  401. if (!dev->reg)
  402. return -ENOMEM;
  403. /* Each supported compatible has some RSTOUT register quirk */
  404. if (of_device_is_compatible(node, "marvell,orion-wdt")) {
  405. dev->rstout = orion_wdt_ioremap_rstout(pdev, res->start &
  406. INTERNAL_REGS_MASK);
  407. if (!dev->rstout)
  408. return -ENODEV;
  409. } else if (of_device_is_compatible(node, "marvell,armada-370-wdt") ||
  410. of_device_is_compatible(node, "marvell,armada-xp-wdt")) {
  411. /* Dedicated RSTOUT register, can be requested. */
  412. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  413. dev->rstout = devm_ioremap_resource(&pdev->dev, res);
  414. if (IS_ERR(dev->rstout))
  415. return PTR_ERR(dev->rstout);
  416. } else if (of_device_is_compatible(node, "marvell,armada-375-wdt") ||
  417. of_device_is_compatible(node, "marvell,armada-380-wdt")) {
  418. /* Dedicated RSTOUT register, can be requested. */
  419. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  420. dev->rstout = devm_ioremap_resource(&pdev->dev, res);
  421. if (IS_ERR(dev->rstout))
  422. return PTR_ERR(dev->rstout);
  423. res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
  424. if (!res)
  425. return -ENODEV;
  426. dev->rstout_mask = devm_ioremap(&pdev->dev, res->start,
  427. resource_size(res));
  428. if (!dev->rstout_mask)
  429. return -ENOMEM;
  430. } else {
  431. return -ENODEV;
  432. }
  433. return 0;
  434. }
  435. static int orion_wdt_probe(struct platform_device *pdev)
  436. {
  437. struct orion_watchdog *dev;
  438. const struct of_device_id *match;
  439. unsigned int wdt_max_duration; /* (seconds) */
  440. int ret, irq;
  441. dev = devm_kzalloc(&pdev->dev, sizeof(struct orion_watchdog),
  442. GFP_KERNEL);
  443. if (!dev)
  444. return -ENOMEM;
  445. match = of_match_device(orion_wdt_of_match_table, &pdev->dev);
  446. if (!match)
  447. /* Default legacy match */
  448. match = &orion_wdt_of_match_table[0];
  449. dev->wdt.info = &orion_wdt_info;
  450. dev->wdt.ops = &orion_wdt_ops;
  451. dev->wdt.min_timeout = 1;
  452. dev->data = match->data;
  453. ret = orion_wdt_get_regs(pdev, dev);
  454. if (ret)
  455. return ret;
  456. ret = dev->data->clock_init(pdev, dev);
  457. if (ret) {
  458. dev_err(&pdev->dev, "cannot initialize clock\n");
  459. return ret;
  460. }
  461. wdt_max_duration = WDT_MAX_CYCLE_COUNT / dev->clk_rate;
  462. dev->wdt.timeout = wdt_max_duration;
  463. dev->wdt.max_timeout = wdt_max_duration;
  464. dev->wdt.parent = &pdev->dev;
  465. watchdog_init_timeout(&dev->wdt, heartbeat, &pdev->dev);
  466. platform_set_drvdata(pdev, &dev->wdt);
  467. watchdog_set_drvdata(&dev->wdt, dev);
  468. /*
  469. * Let's make sure the watchdog is fully stopped, unless it's
  470. * explicitly enabled. This may be the case if the module was
  471. * removed and re-insterted, or if the bootloader explicitly
  472. * set a running watchdog before booting the kernel.
  473. */
  474. if (!orion_wdt_enabled(&dev->wdt))
  475. orion_wdt_stop(&dev->wdt);
  476. /* Request the IRQ only after the watchdog is disabled */
  477. irq = platform_get_irq(pdev, 0);
  478. if (irq > 0) {
  479. /*
  480. * Not all supported platforms specify an interrupt for the
  481. * watchdog, so let's make it optional.
  482. */
  483. ret = devm_request_irq(&pdev->dev, irq, orion_wdt_irq, 0,
  484. pdev->name, dev);
  485. if (ret < 0) {
  486. dev_err(&pdev->dev, "failed to request IRQ\n");
  487. goto disable_clk;
  488. }
  489. }
  490. watchdog_set_nowayout(&dev->wdt, nowayout);
  491. ret = watchdog_register_device(&dev->wdt);
  492. if (ret)
  493. goto disable_clk;
  494. pr_info("Initial timeout %d sec%s\n",
  495. dev->wdt.timeout, nowayout ? ", nowayout" : "");
  496. return 0;
  497. disable_clk:
  498. clk_disable_unprepare(dev->clk);
  499. clk_put(dev->clk);
  500. return ret;
  501. }
  502. static int orion_wdt_remove(struct platform_device *pdev)
  503. {
  504. struct watchdog_device *wdt_dev = platform_get_drvdata(pdev);
  505. struct orion_watchdog *dev = watchdog_get_drvdata(wdt_dev);
  506. watchdog_unregister_device(wdt_dev);
  507. clk_disable_unprepare(dev->clk);
  508. clk_put(dev->clk);
  509. return 0;
  510. }
  511. static void orion_wdt_shutdown(struct platform_device *pdev)
  512. {
  513. struct watchdog_device *wdt_dev = platform_get_drvdata(pdev);
  514. orion_wdt_stop(wdt_dev);
  515. }
  516. static struct platform_driver orion_wdt_driver = {
  517. .probe = orion_wdt_probe,
  518. .remove = orion_wdt_remove,
  519. .shutdown = orion_wdt_shutdown,
  520. .driver = {
  521. .name = "orion_wdt",
  522. .of_match_table = orion_wdt_of_match_table,
  523. },
  524. };
  525. module_platform_driver(orion_wdt_driver);
  526. MODULE_AUTHOR("Sylver Bruneau <sylver.bruneau@googlemail.com>");
  527. MODULE_DESCRIPTION("Orion Processor Watchdog");
  528. module_param(heartbeat, int, 0);
  529. MODULE_PARM_DESC(heartbeat, "Initial watchdog heartbeat in seconds");
  530. module_param(nowayout, bool, 0);
  531. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  532. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  533. MODULE_LICENSE("GPL");
  534. MODULE_ALIAS("platform:orion_wdt");