via_wdt.c 7.5 KB

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  1. /*
  2. * VIA Chipset Watchdog Driver
  3. *
  4. * Copyright (C) 2011 Sigfox
  5. * License terms: GNU General Public License (GPL) version 2
  6. * Author: Marc Vertes <marc.vertes@sigfox.com>
  7. * Based on a preliminary version from Harald Welte <HaraldWelte@viatech.com>
  8. * Timer code by Wim Van Sebroeck <wim@iguana.be>
  9. *
  10. * Caveat: PnP must be enabled in BIOS to allow full access to watchdog
  11. * control registers. If not, the watchdog must be configured in BIOS manually.
  12. */
  13. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14. #include <linux/device.h>
  15. #include <linux/io.h>
  16. #include <linux/jiffies.h>
  17. #include <linux/module.h>
  18. #include <linux/pci.h>
  19. #include <linux/timer.h>
  20. #include <linux/watchdog.h>
  21. /* Configuration registers relative to the pci device */
  22. #define VIA_WDT_MMIO_BASE 0xe8 /* MMIO region base address */
  23. #define VIA_WDT_CONF 0xec /* watchdog enable state */
  24. /* Relevant bits for the VIA_WDT_CONF register */
  25. #define VIA_WDT_CONF_ENABLE 0x01 /* 1: enable watchdog */
  26. #define VIA_WDT_CONF_MMIO 0x02 /* 1: enable watchdog MMIO */
  27. /*
  28. * The MMIO region contains the watchog control register and the
  29. * hardware timer counter.
  30. */
  31. #define VIA_WDT_MMIO_LEN 8 /* MMIO region length in bytes */
  32. #define VIA_WDT_CTL 0 /* MMIO addr+0: state/control reg. */
  33. #define VIA_WDT_COUNT 4 /* MMIO addr+4: timer counter reg. */
  34. /* Bits for the VIA_WDT_CTL register */
  35. #define VIA_WDT_RUNNING 0x01 /* 0: stop, 1: running */
  36. #define VIA_WDT_FIRED 0x02 /* 1: restarted by expired watchdog */
  37. #define VIA_WDT_PWROFF 0x04 /* 0: reset, 1: poweroff */
  38. #define VIA_WDT_DISABLED 0x08 /* 1: timer is disabled */
  39. #define VIA_WDT_TRIGGER 0x80 /* 1: start a new countdown */
  40. /* Hardware heartbeat in seconds */
  41. #define WDT_HW_HEARTBEAT 1
  42. /* Timer heartbeat (500ms) */
  43. #define WDT_HEARTBEAT (HZ/2) /* should be <= ((WDT_HW_HEARTBEAT*HZ)/2) */
  44. /* User space timeout in seconds */
  45. #define WDT_TIMEOUT_MAX 1023 /* approx. 17 min. */
  46. #define WDT_TIMEOUT 60
  47. static int timeout = WDT_TIMEOUT;
  48. module_param(timeout, int, 0);
  49. MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds, between 1 and 1023 "
  50. "(default = " __MODULE_STRING(WDT_TIMEOUT) ")");
  51. static bool nowayout = WATCHDOG_NOWAYOUT;
  52. module_param(nowayout, bool, 0);
  53. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
  54. "(default = " __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  55. static struct watchdog_device wdt_dev;
  56. static struct resource wdt_res;
  57. static void __iomem *wdt_mem;
  58. static unsigned int mmio;
  59. static void wdt_timer_tick(unsigned long data);
  60. static DEFINE_TIMER(timer, wdt_timer_tick, 0, 0);
  61. /* The timer that pings the watchdog */
  62. static unsigned long next_heartbeat; /* the next_heartbeat for the timer */
  63. static inline void wdt_reset(void)
  64. {
  65. unsigned int ctl = readl(wdt_mem);
  66. writel(ctl | VIA_WDT_TRIGGER, wdt_mem);
  67. }
  68. /*
  69. * Timer tick: the timer will make sure that the watchdog timer hardware
  70. * is being reset in time. The conditions to do this are:
  71. * 1) the watchog timer has been started and /dev/watchdog is open
  72. * and there is still time left before userspace should send the
  73. * next heartbeat/ping. (note: the internal heartbeat is much smaller
  74. * then the external/userspace heartbeat).
  75. * 2) the watchdog timer has been stopped by userspace.
  76. */
  77. static void wdt_timer_tick(unsigned long data)
  78. {
  79. if (time_before(jiffies, next_heartbeat) ||
  80. (!watchdog_active(&wdt_dev))) {
  81. wdt_reset();
  82. mod_timer(&timer, jiffies + WDT_HEARTBEAT);
  83. } else
  84. pr_crit("I will reboot your machine !\n");
  85. }
  86. static int wdt_ping(struct watchdog_device *wdd)
  87. {
  88. /* calculate when the next userspace timeout will be */
  89. next_heartbeat = jiffies + wdd->timeout * HZ;
  90. return 0;
  91. }
  92. static int wdt_start(struct watchdog_device *wdd)
  93. {
  94. unsigned int ctl = readl(wdt_mem);
  95. writel(wdd->timeout, wdt_mem + VIA_WDT_COUNT);
  96. writel(ctl | VIA_WDT_RUNNING | VIA_WDT_TRIGGER, wdt_mem);
  97. wdt_ping(wdd);
  98. mod_timer(&timer, jiffies + WDT_HEARTBEAT);
  99. return 0;
  100. }
  101. static int wdt_stop(struct watchdog_device *wdd)
  102. {
  103. unsigned int ctl = readl(wdt_mem);
  104. writel(ctl & ~VIA_WDT_RUNNING, wdt_mem);
  105. return 0;
  106. }
  107. static int wdt_set_timeout(struct watchdog_device *wdd,
  108. unsigned int new_timeout)
  109. {
  110. writel(new_timeout, wdt_mem + VIA_WDT_COUNT);
  111. wdd->timeout = new_timeout;
  112. return 0;
  113. }
  114. static const struct watchdog_info wdt_info = {
  115. .identity = "VIA watchdog",
  116. .options = WDIOF_CARDRESET |
  117. WDIOF_SETTIMEOUT |
  118. WDIOF_MAGICCLOSE |
  119. WDIOF_KEEPALIVEPING,
  120. };
  121. static const struct watchdog_ops wdt_ops = {
  122. .owner = THIS_MODULE,
  123. .start = wdt_start,
  124. .stop = wdt_stop,
  125. .ping = wdt_ping,
  126. .set_timeout = wdt_set_timeout,
  127. };
  128. static struct watchdog_device wdt_dev = {
  129. .info = &wdt_info,
  130. .ops = &wdt_ops,
  131. .min_timeout = 1,
  132. .max_timeout = WDT_TIMEOUT_MAX,
  133. };
  134. static int wdt_probe(struct pci_dev *pdev,
  135. const struct pci_device_id *ent)
  136. {
  137. unsigned char conf;
  138. int ret = -ENODEV;
  139. if (pci_enable_device(pdev)) {
  140. dev_err(&pdev->dev, "cannot enable PCI device\n");
  141. return -ENODEV;
  142. }
  143. /*
  144. * Allocate a MMIO region which contains watchdog control register
  145. * and counter, then configure the watchdog to use this region.
  146. * This is possible only if PnP is properly enabled in BIOS.
  147. * If not, the watchdog must be configured in BIOS manually.
  148. */
  149. if (allocate_resource(&iomem_resource, &wdt_res, VIA_WDT_MMIO_LEN,
  150. 0xf0000000, 0xffffff00, 0xff, NULL, NULL)) {
  151. dev_err(&pdev->dev, "MMIO allocation failed\n");
  152. goto err_out_disable_device;
  153. }
  154. pci_write_config_dword(pdev, VIA_WDT_MMIO_BASE, wdt_res.start);
  155. pci_read_config_byte(pdev, VIA_WDT_CONF, &conf);
  156. conf |= VIA_WDT_CONF_ENABLE | VIA_WDT_CONF_MMIO;
  157. pci_write_config_byte(pdev, VIA_WDT_CONF, conf);
  158. pci_read_config_dword(pdev, VIA_WDT_MMIO_BASE, &mmio);
  159. if (mmio) {
  160. dev_info(&pdev->dev, "VIA Chipset watchdog MMIO: %x\n", mmio);
  161. } else {
  162. dev_err(&pdev->dev, "MMIO setting failed. Check BIOS.\n");
  163. goto err_out_resource;
  164. }
  165. if (!request_mem_region(mmio, VIA_WDT_MMIO_LEN, "via_wdt")) {
  166. dev_err(&pdev->dev, "MMIO region busy\n");
  167. goto err_out_resource;
  168. }
  169. wdt_mem = ioremap(mmio, VIA_WDT_MMIO_LEN);
  170. if (wdt_mem == NULL) {
  171. dev_err(&pdev->dev, "cannot remap VIA wdt MMIO registers\n");
  172. goto err_out_release;
  173. }
  174. if (timeout < 1 || timeout > WDT_TIMEOUT_MAX)
  175. timeout = WDT_TIMEOUT;
  176. wdt_dev.timeout = timeout;
  177. wdt_dev.parent = &pdev->dev;
  178. watchdog_set_nowayout(&wdt_dev, nowayout);
  179. if (readl(wdt_mem) & VIA_WDT_FIRED)
  180. wdt_dev.bootstatus |= WDIOF_CARDRESET;
  181. ret = watchdog_register_device(&wdt_dev);
  182. if (ret)
  183. goto err_out_iounmap;
  184. /* start triggering, in case of watchdog already enabled by BIOS */
  185. mod_timer(&timer, jiffies + WDT_HEARTBEAT);
  186. return 0;
  187. err_out_iounmap:
  188. iounmap(wdt_mem);
  189. err_out_release:
  190. release_mem_region(mmio, VIA_WDT_MMIO_LEN);
  191. err_out_resource:
  192. release_resource(&wdt_res);
  193. err_out_disable_device:
  194. pci_disable_device(pdev);
  195. return ret;
  196. }
  197. static void wdt_remove(struct pci_dev *pdev)
  198. {
  199. watchdog_unregister_device(&wdt_dev);
  200. del_timer_sync(&timer);
  201. iounmap(wdt_mem);
  202. release_mem_region(mmio, VIA_WDT_MMIO_LEN);
  203. release_resource(&wdt_res);
  204. pci_disable_device(pdev);
  205. }
  206. static const struct pci_device_id wdt_pci_table[] = {
  207. { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CX700) },
  208. { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX800) },
  209. { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855) },
  210. { 0 }
  211. };
  212. static struct pci_driver wdt_driver = {
  213. .name = "via_wdt",
  214. .id_table = wdt_pci_table,
  215. .probe = wdt_probe,
  216. .remove = wdt_remove,
  217. };
  218. module_pci_driver(wdt_driver);
  219. MODULE_AUTHOR("Marc Vertes");
  220. MODULE_DESCRIPTION("Driver for watchdog timer on VIA chipset");
  221. MODULE_LICENSE("GPL");