altr,rst-mgr.h 2.2 KB

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  1. /*
  2. * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
  3. *
  4. * This software is licensed under the terms of the GNU General Public
  5. * License version 2, as published by the Free Software Foundation, and
  6. * may be copied, distributed, and modified under those terms.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
  14. #define _DT_BINDINGS_RESET_ALTR_RST_MGR_H
  15. /* MPUMODRST */
  16. #define CPU0_RESET 0
  17. #define CPU1_RESET 1
  18. #define WDS_RESET 2
  19. #define SCUPER_RESET 3
  20. #define L2_RESET 4
  21. /* PERMODRST */
  22. #define EMAC0_RESET 32
  23. #define EMAC1_RESET 33
  24. #define USB0_RESET 34
  25. #define USB1_RESET 35
  26. #define NAND_RESET 36
  27. #define QSPI_RESET 37
  28. #define L4WD0_RESET 38
  29. #define L4WD1_RESET 39
  30. #define OSC1TIMER0_RESET 40
  31. #define OSC1TIMER1_RESET 41
  32. #define SPTIMER0_RESET 42
  33. #define SPTIMER1_RESET 43
  34. #define I2C0_RESET 44
  35. #define I2C1_RESET 45
  36. #define I2C2_RESET 46
  37. #define I2C3_RESET 47
  38. #define UART0_RESET 48
  39. #define UART1_RESET 49
  40. #define SPIM0_RESET 50
  41. #define SPIM1_RESET 51
  42. #define SPIS0_RESET 52
  43. #define SPIS1_RESET 53
  44. #define SDMMC_RESET 54
  45. #define CAN0_RESET 55
  46. #define CAN1_RESET 56
  47. #define GPIO0_RESET 57
  48. #define GPIO1_RESET 58
  49. #define GPIO2_RESET 59
  50. #define DMA_RESET 60
  51. #define SDR_RESET 61
  52. /* PER2MODRST */
  53. #define DMAIF0_RESET 64
  54. #define DMAIF1_RESET 65
  55. #define DMAIF2_RESET 66
  56. #define DMAIF3_RESET 67
  57. #define DMAIF4_RESET 68
  58. #define DMAIF5_RESET 69
  59. #define DMAIF6_RESET 70
  60. #define DMAIF7_RESET 71
  61. /* BRGMODRST */
  62. #define HPS2FPGA_RESET 96
  63. #define LWHPS2FPGA_RESET 97
  64. #define FPGA2HPS_RESET 98
  65. /* MISCMODRST*/
  66. #define ROM_RESET 128
  67. #define OCRAM_RESET 129
  68. #define SYSMGR_RESET 130
  69. #define SYSMGRCOLD_RESET 131
  70. #define FPGAMGR_RESET 132
  71. #define ACPIDMAP_RESET 133
  72. #define S2F_RESET 134
  73. #define S2FCOLD_RESET 135
  74. #define NRSTPIN_RESET 136
  75. #define TIMESTAMPCOLD_RESET 137
  76. #define CLKMGRCOLD_RESET 138
  77. #define SCANMGR_RESET 139
  78. #define FRZCTRLCOLD_RESET 140
  79. #define SYSDBG_RESET 141
  80. #define DBG_RESET 142
  81. #define TAPCOLD_RESET 143
  82. #define SDRCOLD_RESET 144
  83. #endif