dma-dw.h 2.1 KB

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  1. /*
  2. * Driver for the Synopsys DesignWare DMA Controller
  3. *
  4. * Copyright (C) 2007 Atmel Corporation
  5. * Copyright (C) 2010-2011 ST Microelectronics
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #ifndef _PLATFORM_DATA_DMA_DW_H
  12. #define _PLATFORM_DATA_DMA_DW_H
  13. #include <linux/device.h>
  14. #define DW_DMA_MAX_NR_MASTERS 4
  15. /**
  16. * struct dw_dma_slave - Controller-specific information about a slave
  17. *
  18. * @dma_dev: required DMA master device
  19. * @src_id: src request line
  20. * @dst_id: dst request line
  21. * @src_master: src master for transfers on allocated channel.
  22. * @dst_master: dest master for transfers on allocated channel.
  23. */
  24. struct dw_dma_slave {
  25. struct device *dma_dev;
  26. u8 src_id;
  27. u8 dst_id;
  28. u8 src_master;
  29. u8 dst_master;
  30. };
  31. /**
  32. * struct dw_dma_platform_data - Controller configuration parameters
  33. * @nr_channels: Number of channels supported by hardware (max 8)
  34. * @is_private: The device channels should be marked as private and not for
  35. * by the general purpose DMA channel allocator.
  36. * @is_memcpy: The device channels do support memory-to-memory transfers.
  37. * @chan_allocation_order: Allocate channels starting from 0 or 7
  38. * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
  39. * @block_size: Maximum block size supported by the controller
  40. * @nr_masters: Number of AHB masters supported by the controller
  41. * @data_width: Maximum data width supported by hardware per AHB master
  42. * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
  43. */
  44. struct dw_dma_platform_data {
  45. unsigned int nr_channels;
  46. bool is_private;
  47. bool is_memcpy;
  48. #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
  49. #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
  50. unsigned char chan_allocation_order;
  51. #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
  52. #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
  53. unsigned char chan_priority;
  54. unsigned short block_size;
  55. unsigned char nr_masters;
  56. unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
  57. };
  58. #endif /* _PLATFORM_DATA_DMA_DW_H */