shdma-base.h 4.4 KB

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  1. /*
  2. * Dmaengine driver base library for DMA controllers, found on SH-based SoCs
  3. *
  4. * extracted from shdma.c and headers
  5. *
  6. * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  7. * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
  8. * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
  9. * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
  10. *
  11. * This is free software; you can redistribute it and/or modify
  12. * it under the terms of version 2 of the GNU General Public License as
  13. * published by the Free Software Foundation.
  14. */
  15. #ifndef SHDMA_BASE_H
  16. #define SHDMA_BASE_H
  17. #include <linux/dmaengine.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/list.h>
  20. #include <linux/types.h>
  21. /**
  22. * shdma_pm_state - DMA channel PM state
  23. * SHDMA_PM_ESTABLISHED: either idle or during data transfer
  24. * SHDMA_PM_BUSY: during the transfer preparation, when we have to
  25. * drop the lock temporarily
  26. * SHDMA_PM_PENDING: transfers pending
  27. */
  28. enum shdma_pm_state {
  29. SHDMA_PM_ESTABLISHED,
  30. SHDMA_PM_BUSY,
  31. SHDMA_PM_PENDING,
  32. };
  33. struct device;
  34. /*
  35. * Drivers, using this library are expected to embed struct shdma_dev,
  36. * struct shdma_chan, struct shdma_desc, and struct shdma_slave
  37. * in their respective device, channel, descriptor and slave objects.
  38. */
  39. struct shdma_slave {
  40. int slave_id;
  41. };
  42. struct shdma_desc {
  43. struct list_head node;
  44. struct dma_async_tx_descriptor async_tx;
  45. enum dma_transfer_direction direction;
  46. size_t partial;
  47. dma_cookie_t cookie;
  48. int chunks;
  49. int mark;
  50. bool cyclic; /* used as cyclic transfer */
  51. };
  52. struct shdma_chan {
  53. spinlock_t chan_lock; /* Channel operation lock */
  54. struct list_head ld_queue; /* Link descriptors queue */
  55. struct list_head ld_free; /* Free link descriptors */
  56. struct dma_chan dma_chan; /* DMA channel */
  57. struct device *dev; /* Channel device */
  58. void *desc; /* buffer for descriptor array */
  59. int desc_num; /* desc count */
  60. size_t max_xfer_len; /* max transfer length */
  61. int id; /* Raw id of this channel */
  62. int irq; /* Channel IRQ */
  63. int slave_id; /* Client ID for slave DMA */
  64. int real_slave_id; /* argument passed to filter function */
  65. int hw_req; /* DMA request line for slave DMA - same
  66. * as MID/RID, used with DT */
  67. enum shdma_pm_state pm_state;
  68. };
  69. /**
  70. * struct shdma_ops - simple DMA driver operations
  71. * desc_completed: return true, if this is the descriptor, that just has
  72. * completed (atomic)
  73. * halt_channel: stop DMA channel operation (atomic)
  74. * channel_busy: return true, if the channel is busy (atomic)
  75. * slave_addr: return slave DMA address
  76. * desc_setup: set up the hardware specific descriptor portion (atomic)
  77. * set_slave: bind channel to a slave
  78. * setup_xfer: configure channel hardware for operation (atomic)
  79. * start_xfer: start the DMA transfer (atomic)
  80. * embedded_desc: return Nth struct shdma_desc pointer from the
  81. * descriptor array
  82. * chan_irq: process channel IRQ, return true if a transfer has
  83. * completed (atomic)
  84. */
  85. struct shdma_ops {
  86. bool (*desc_completed)(struct shdma_chan *, struct shdma_desc *);
  87. void (*halt_channel)(struct shdma_chan *);
  88. bool (*channel_busy)(struct shdma_chan *);
  89. dma_addr_t (*slave_addr)(struct shdma_chan *);
  90. int (*desc_setup)(struct shdma_chan *, struct shdma_desc *,
  91. dma_addr_t, dma_addr_t, size_t *);
  92. int (*set_slave)(struct shdma_chan *, int, dma_addr_t, bool);
  93. void (*setup_xfer)(struct shdma_chan *, int);
  94. void (*start_xfer)(struct shdma_chan *, struct shdma_desc *);
  95. struct shdma_desc *(*embedded_desc)(void *, int);
  96. bool (*chan_irq)(struct shdma_chan *, int);
  97. size_t (*get_partial)(struct shdma_chan *, struct shdma_desc *);
  98. };
  99. struct shdma_dev {
  100. struct dma_device dma_dev;
  101. struct shdma_chan **schan;
  102. const struct shdma_ops *ops;
  103. size_t desc_size;
  104. };
  105. #define shdma_for_each_chan(c, d, i) for (i = 0, c = (d)->schan[0]; \
  106. i < (d)->dma_dev.chancnt; c = (d)->schan[++i])
  107. int shdma_request_irq(struct shdma_chan *, int,
  108. unsigned long, const char *);
  109. bool shdma_reset(struct shdma_dev *sdev);
  110. void shdma_chan_probe(struct shdma_dev *sdev,
  111. struct shdma_chan *schan, int id);
  112. void shdma_chan_remove(struct shdma_chan *schan);
  113. int shdma_init(struct device *dev, struct shdma_dev *sdev,
  114. int chan_num);
  115. void shdma_cleanup(struct shdma_dev *sdev);
  116. #if IS_ENABLED(CONFIG_SH_DMAE_BASE)
  117. bool shdma_chan_filter(struct dma_chan *chan, void *arg);
  118. #else
  119. static inline bool shdma_chan_filter(struct dma_chan *chan, void *arg)
  120. {
  121. return false;
  122. }
  123. #endif
  124. #endif