exynos_drm.h 8.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350
  1. /* exynos_drm.h
  2. *
  3. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  4. * Authors:
  5. * Inki Dae <inki.dae@samsung.com>
  6. * Joonyoung Shim <jy0922.shim@samsung.com>
  7. * Seung-Woo Kim <sw0312.kim@samsung.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. #ifndef _UAPI_EXYNOS_DRM_H_
  15. #define _UAPI_EXYNOS_DRM_H_
  16. #include <drm/drm.h>
  17. /**
  18. * User-desired buffer creation information structure.
  19. *
  20. * @size: user-desired memory allocation size.
  21. * - this size value would be page-aligned internally.
  22. * @flags: user request for setting memory type or cache attributes.
  23. * @handle: returned a handle to created gem object.
  24. * - this handle will be set by gem module of kernel side.
  25. */
  26. struct drm_exynos_gem_create {
  27. uint64_t size;
  28. unsigned int flags;
  29. unsigned int handle;
  30. };
  31. /**
  32. * A structure to gem information.
  33. *
  34. * @handle: a handle to gem object created.
  35. * @flags: flag value including memory type and cache attribute and
  36. * this value would be set by driver.
  37. * @size: size to memory region allocated by gem and this size would
  38. * be set by driver.
  39. */
  40. struct drm_exynos_gem_info {
  41. unsigned int handle;
  42. unsigned int flags;
  43. uint64_t size;
  44. };
  45. /**
  46. * A structure for user connection request of virtual display.
  47. *
  48. * @connection: indicate whether doing connetion or not by user.
  49. * @extensions: if this value is 1 then the vidi driver would need additional
  50. * 128bytes edid data.
  51. * @edid: the edid data pointer from user side.
  52. */
  53. struct drm_exynos_vidi_connection {
  54. unsigned int connection;
  55. unsigned int extensions;
  56. uint64_t edid;
  57. };
  58. /* memory type definitions. */
  59. enum e_drm_exynos_gem_mem_type {
  60. /* Physically Continuous memory and used as default. */
  61. EXYNOS_BO_CONTIG = 0 << 0,
  62. /* Physically Non-Continuous memory. */
  63. EXYNOS_BO_NONCONTIG = 1 << 0,
  64. /* non-cachable mapping and used as default. */
  65. EXYNOS_BO_NONCACHABLE = 0 << 1,
  66. /* cachable mapping. */
  67. EXYNOS_BO_CACHABLE = 1 << 1,
  68. /* write-combine mapping. */
  69. EXYNOS_BO_WC = 1 << 2,
  70. EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
  71. EXYNOS_BO_WC
  72. };
  73. struct drm_exynos_g2d_get_ver {
  74. __u32 major;
  75. __u32 minor;
  76. };
  77. struct drm_exynos_g2d_cmd {
  78. __u32 offset;
  79. __u32 data;
  80. };
  81. enum drm_exynos_g2d_buf_type {
  82. G2D_BUF_USERPTR = 1 << 31,
  83. };
  84. enum drm_exynos_g2d_event_type {
  85. G2D_EVENT_NOT,
  86. G2D_EVENT_NONSTOP,
  87. G2D_EVENT_STOP, /* not yet */
  88. };
  89. struct drm_exynos_g2d_userptr {
  90. unsigned long userptr;
  91. unsigned long size;
  92. };
  93. struct drm_exynos_g2d_set_cmdlist {
  94. __u64 cmd;
  95. __u64 cmd_buf;
  96. __u32 cmd_nr;
  97. __u32 cmd_buf_nr;
  98. /* for g2d event */
  99. __u64 event_type;
  100. __u64 user_data;
  101. };
  102. struct drm_exynos_g2d_exec {
  103. __u64 async;
  104. };
  105. enum drm_exynos_ops_id {
  106. EXYNOS_DRM_OPS_SRC,
  107. EXYNOS_DRM_OPS_DST,
  108. EXYNOS_DRM_OPS_MAX,
  109. };
  110. struct drm_exynos_sz {
  111. __u32 hsize;
  112. __u32 vsize;
  113. };
  114. struct drm_exynos_pos {
  115. __u32 x;
  116. __u32 y;
  117. __u32 w;
  118. __u32 h;
  119. };
  120. enum drm_exynos_flip {
  121. EXYNOS_DRM_FLIP_NONE = (0 << 0),
  122. EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
  123. EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
  124. EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL |
  125. EXYNOS_DRM_FLIP_HORIZONTAL,
  126. };
  127. enum drm_exynos_degree {
  128. EXYNOS_DRM_DEGREE_0,
  129. EXYNOS_DRM_DEGREE_90,
  130. EXYNOS_DRM_DEGREE_180,
  131. EXYNOS_DRM_DEGREE_270,
  132. };
  133. enum drm_exynos_planer {
  134. EXYNOS_DRM_PLANAR_Y,
  135. EXYNOS_DRM_PLANAR_CB,
  136. EXYNOS_DRM_PLANAR_CR,
  137. EXYNOS_DRM_PLANAR_MAX,
  138. };
  139. /**
  140. * A structure for ipp supported property list.
  141. *
  142. * @version: version of this structure.
  143. * @ipp_id: id of ipp driver.
  144. * @count: count of ipp driver.
  145. * @writeback: flag of writeback supporting.
  146. * @flip: flag of flip supporting.
  147. * @degree: flag of degree information.
  148. * @csc: flag of csc supporting.
  149. * @crop: flag of crop supporting.
  150. * @scale: flag of scale supporting.
  151. * @refresh_min: min hz of refresh.
  152. * @refresh_max: max hz of refresh.
  153. * @crop_min: crop min resolution.
  154. * @crop_max: crop max resolution.
  155. * @scale_min: scale min resolution.
  156. * @scale_max: scale max resolution.
  157. */
  158. struct drm_exynos_ipp_prop_list {
  159. __u32 version;
  160. __u32 ipp_id;
  161. __u32 count;
  162. __u32 writeback;
  163. __u32 flip;
  164. __u32 degree;
  165. __u32 csc;
  166. __u32 crop;
  167. __u32 scale;
  168. __u32 refresh_min;
  169. __u32 refresh_max;
  170. __u32 reserved;
  171. struct drm_exynos_sz crop_min;
  172. struct drm_exynos_sz crop_max;
  173. struct drm_exynos_sz scale_min;
  174. struct drm_exynos_sz scale_max;
  175. };
  176. /**
  177. * A structure for ipp config.
  178. *
  179. * @ops_id: property of operation directions.
  180. * @flip: property of mirror, flip.
  181. * @degree: property of rotation degree.
  182. * @fmt: property of image format.
  183. * @sz: property of image size.
  184. * @pos: property of image position(src-cropped,dst-scaler).
  185. */
  186. struct drm_exynos_ipp_config {
  187. enum drm_exynos_ops_id ops_id;
  188. enum drm_exynos_flip flip;
  189. enum drm_exynos_degree degree;
  190. __u32 fmt;
  191. struct drm_exynos_sz sz;
  192. struct drm_exynos_pos pos;
  193. };
  194. enum drm_exynos_ipp_cmd {
  195. IPP_CMD_NONE,
  196. IPP_CMD_M2M,
  197. IPP_CMD_WB,
  198. IPP_CMD_OUTPUT,
  199. IPP_CMD_MAX,
  200. };
  201. /**
  202. * A structure for ipp property.
  203. *
  204. * @config: source, destination config.
  205. * @cmd: definition of command.
  206. * @ipp_id: id of ipp driver.
  207. * @prop_id: id of property.
  208. * @refresh_rate: refresh rate.
  209. */
  210. struct drm_exynos_ipp_property {
  211. struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
  212. enum drm_exynos_ipp_cmd cmd;
  213. __u32 ipp_id;
  214. __u32 prop_id;
  215. __u32 refresh_rate;
  216. };
  217. enum drm_exynos_ipp_buf_type {
  218. IPP_BUF_ENQUEUE,
  219. IPP_BUF_DEQUEUE,
  220. };
  221. /**
  222. * A structure for ipp buffer operations.
  223. *
  224. * @ops_id: operation directions.
  225. * @buf_type: definition of buffer.
  226. * @prop_id: id of property.
  227. * @buf_id: id of buffer.
  228. * @handle: Y, Cb, Cr each planar handle.
  229. * @user_data: user data.
  230. */
  231. struct drm_exynos_ipp_queue_buf {
  232. enum drm_exynos_ops_id ops_id;
  233. enum drm_exynos_ipp_buf_type buf_type;
  234. __u32 prop_id;
  235. __u32 buf_id;
  236. __u32 handle[EXYNOS_DRM_PLANAR_MAX];
  237. __u32 reserved;
  238. __u64 user_data;
  239. };
  240. enum drm_exynos_ipp_ctrl {
  241. IPP_CTRL_PLAY,
  242. IPP_CTRL_STOP,
  243. IPP_CTRL_PAUSE,
  244. IPP_CTRL_RESUME,
  245. IPP_CTRL_MAX,
  246. };
  247. /**
  248. * A structure for ipp start/stop operations.
  249. *
  250. * @prop_id: id of property.
  251. * @ctrl: definition of control.
  252. */
  253. struct drm_exynos_ipp_cmd_ctrl {
  254. __u32 prop_id;
  255. enum drm_exynos_ipp_ctrl ctrl;
  256. };
  257. #define DRM_EXYNOS_GEM_CREATE 0x00
  258. /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
  259. #define DRM_EXYNOS_GEM_GET 0x04
  260. #define DRM_EXYNOS_VIDI_CONNECTION 0x07
  261. /* G2D */
  262. #define DRM_EXYNOS_G2D_GET_VER 0x20
  263. #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
  264. #define DRM_EXYNOS_G2D_EXEC 0x22
  265. /* IPP - Image Post Processing */
  266. #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30
  267. #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31
  268. #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32
  269. #define DRM_EXYNOS_IPP_CMD_CTRL 0x33
  270. #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
  271. DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
  272. #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
  273. DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
  274. #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
  275. DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
  276. #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
  277. DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
  278. #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
  279. DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
  280. #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
  281. DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
  282. #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
  283. DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
  284. #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
  285. DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
  286. #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \
  287. DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
  288. #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \
  289. DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
  290. /* EXYNOS specific events */
  291. #define DRM_EXYNOS_G2D_EVENT 0x80000000
  292. #define DRM_EXYNOS_IPP_EVENT 0x80000001
  293. struct drm_exynos_g2d_event {
  294. struct drm_event base;
  295. __u64 user_data;
  296. __u32 tv_sec;
  297. __u32 tv_usec;
  298. __u32 cmdlist_no;
  299. __u32 reserved;
  300. };
  301. struct drm_exynos_ipp_event {
  302. struct drm_event base;
  303. __u64 user_data;
  304. __u32 tv_sec;
  305. __u32 tv_usec;
  306. __u32 prop_id;
  307. __u32 reserved;
  308. __u32 buf_id[EXYNOS_DRM_OPS_MAX];
  309. };
  310. #endif /* _UAPI_EXYNOS_DRM_H_ */