pxa2xx-ac97-lib.c 8.7 KB

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  1. /*
  2. * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
  3. * which contain:
  4. *
  5. * Author: Nicolas Pitre
  6. * Created: Dec 02, 2004
  7. * Copyright: MontaVista Software Inc.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/clk.h>
  17. #include <linux/delay.h>
  18. #include <linux/module.h>
  19. #include <linux/io.h>
  20. #include <linux/gpio.h>
  21. #include <sound/ac97_codec.h>
  22. #include <sound/pxa2xx-lib.h>
  23. #include <mach/irqs.h>
  24. #include <mach/regs-ac97.h>
  25. #include <mach/audio.h>
  26. static DEFINE_MUTEX(car_mutex);
  27. static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
  28. static volatile long gsr_bits;
  29. static struct clk *ac97_clk;
  30. static struct clk *ac97conf_clk;
  31. static int reset_gpio;
  32. extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
  33. /*
  34. * Beware PXA27x bugs:
  35. *
  36. * o Slot 12 read from modem space will hang controller.
  37. * o CDONE, SDONE interrupt fails after any slot 12 IO.
  38. *
  39. * We therefore have an hybrid approach for waiting on SDONE (interrupt or
  40. * 1 jiffy timeout if interrupt never comes).
  41. */
  42. unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  43. {
  44. unsigned short val = -1;
  45. volatile u32 *reg_addr;
  46. mutex_lock(&car_mutex);
  47. /* set up primary or secondary codec space */
  48. if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
  49. reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
  50. else
  51. reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
  52. reg_addr += (reg >> 1);
  53. /* start read access across the ac97 link */
  54. GSR = GSR_CDONE | GSR_SDONE;
  55. gsr_bits = 0;
  56. val = *reg_addr;
  57. if (reg == AC97_GPIO_STATUS)
  58. goto out;
  59. if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
  60. !((GSR | gsr_bits) & GSR_SDONE)) {
  61. printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
  62. __func__, reg, GSR | gsr_bits);
  63. val = -1;
  64. goto out;
  65. }
  66. /* valid data now */
  67. GSR = GSR_CDONE | GSR_SDONE;
  68. gsr_bits = 0;
  69. val = *reg_addr;
  70. /* but we've just started another cycle... */
  71. wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
  72. out: mutex_unlock(&car_mutex);
  73. return val;
  74. }
  75. EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
  76. void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  77. unsigned short val)
  78. {
  79. volatile u32 *reg_addr;
  80. mutex_lock(&car_mutex);
  81. /* set up primary or secondary codec space */
  82. if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
  83. reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
  84. else
  85. reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
  86. reg_addr += (reg >> 1);
  87. GSR = GSR_CDONE | GSR_SDONE;
  88. gsr_bits = 0;
  89. *reg_addr = val;
  90. if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
  91. !((GSR | gsr_bits) & GSR_CDONE))
  92. printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
  93. __func__, reg, GSR | gsr_bits);
  94. mutex_unlock(&car_mutex);
  95. }
  96. EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
  97. #ifdef CONFIG_PXA25x
  98. static inline void pxa_ac97_warm_pxa25x(void)
  99. {
  100. gsr_bits = 0;
  101. GCR |= GCR_WARM_RST;
  102. }
  103. static inline void pxa_ac97_cold_pxa25x(void)
  104. {
  105. GCR &= GCR_COLD_RST; /* clear everything but nCRST */
  106. GCR &= ~GCR_COLD_RST; /* then assert nCRST */
  107. gsr_bits = 0;
  108. GCR = GCR_COLD_RST;
  109. }
  110. #endif
  111. #ifdef CONFIG_PXA27x
  112. static inline void pxa_ac97_warm_pxa27x(void)
  113. {
  114. gsr_bits = 0;
  115. /* warm reset broken on Bulverde, so manually keep AC97 reset high */
  116. pxa27x_configure_ac97reset(reset_gpio, true);
  117. udelay(10);
  118. GCR |= GCR_WARM_RST;
  119. pxa27x_configure_ac97reset(reset_gpio, false);
  120. udelay(500);
  121. }
  122. static inline void pxa_ac97_cold_pxa27x(void)
  123. {
  124. GCR &= GCR_COLD_RST; /* clear everything but nCRST */
  125. GCR &= ~GCR_COLD_RST; /* then assert nCRST */
  126. gsr_bits = 0;
  127. /* PXA27x Developers Manual section 13.5.2.2.1 */
  128. clk_prepare_enable(ac97conf_clk);
  129. udelay(5);
  130. clk_disable_unprepare(ac97conf_clk);
  131. GCR = GCR_COLD_RST | GCR_WARM_RST;
  132. }
  133. #endif
  134. #ifdef CONFIG_PXA3xx
  135. static inline void pxa_ac97_warm_pxa3xx(void)
  136. {
  137. gsr_bits = 0;
  138. /* Can't use interrupts */
  139. GCR |= GCR_WARM_RST;
  140. }
  141. static inline void pxa_ac97_cold_pxa3xx(void)
  142. {
  143. /* Hold CLKBPB for 100us */
  144. GCR = 0;
  145. GCR = GCR_CLKBPB;
  146. udelay(100);
  147. GCR = 0;
  148. GCR &= GCR_COLD_RST; /* clear everything but nCRST */
  149. GCR &= ~GCR_COLD_RST; /* then assert nCRST */
  150. gsr_bits = 0;
  151. /* Can't use interrupts on PXA3xx */
  152. GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
  153. GCR = GCR_WARM_RST | GCR_COLD_RST;
  154. }
  155. #endif
  156. bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
  157. {
  158. unsigned long gsr;
  159. unsigned int timeout = 100;
  160. #ifdef CONFIG_PXA25x
  161. if (cpu_is_pxa25x())
  162. pxa_ac97_warm_pxa25x();
  163. else
  164. #endif
  165. #ifdef CONFIG_PXA27x
  166. if (cpu_is_pxa27x())
  167. pxa_ac97_warm_pxa27x();
  168. else
  169. #endif
  170. #ifdef CONFIG_PXA3xx
  171. if (cpu_is_pxa3xx())
  172. pxa_ac97_warm_pxa3xx();
  173. else
  174. #endif
  175. snd_BUG();
  176. while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
  177. mdelay(1);
  178. gsr = GSR | gsr_bits;
  179. if (!(gsr & (GSR_PCR | GSR_SCR))) {
  180. printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
  181. __func__, gsr);
  182. return false;
  183. }
  184. return true;
  185. }
  186. EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
  187. bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
  188. {
  189. unsigned long gsr;
  190. unsigned int timeout = 1000;
  191. #ifdef CONFIG_PXA25x
  192. if (cpu_is_pxa25x())
  193. pxa_ac97_cold_pxa25x();
  194. else
  195. #endif
  196. #ifdef CONFIG_PXA27x
  197. if (cpu_is_pxa27x())
  198. pxa_ac97_cold_pxa27x();
  199. else
  200. #endif
  201. #ifdef CONFIG_PXA3xx
  202. if (cpu_is_pxa3xx())
  203. pxa_ac97_cold_pxa3xx();
  204. else
  205. #endif
  206. snd_BUG();
  207. while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
  208. mdelay(1);
  209. gsr = GSR | gsr_bits;
  210. if (!(gsr & (GSR_PCR | GSR_SCR))) {
  211. printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
  212. __func__, gsr);
  213. return false;
  214. }
  215. return true;
  216. }
  217. EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
  218. void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
  219. {
  220. GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
  221. GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
  222. }
  223. EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
  224. static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
  225. {
  226. long status;
  227. status = GSR;
  228. if (status) {
  229. GSR = status;
  230. gsr_bits |= status;
  231. wake_up(&gsr_wq);
  232. /* Although we don't use those we still need to clear them
  233. since they tend to spuriously trigger when MMC is used
  234. (hardware bug? go figure)... */
  235. if (cpu_is_pxa27x()) {
  236. MISR = MISR_EOC;
  237. PISR = PISR_EOC;
  238. MCSR = MCSR_EOC;
  239. }
  240. return IRQ_HANDLED;
  241. }
  242. return IRQ_NONE;
  243. }
  244. #ifdef CONFIG_PM
  245. int pxa2xx_ac97_hw_suspend(void)
  246. {
  247. GCR |= GCR_ACLINK_OFF;
  248. clk_disable_unprepare(ac97_clk);
  249. return 0;
  250. }
  251. EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
  252. int pxa2xx_ac97_hw_resume(void)
  253. {
  254. clk_prepare_enable(ac97_clk);
  255. return 0;
  256. }
  257. EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
  258. #endif
  259. int pxa2xx_ac97_hw_probe(struct platform_device *dev)
  260. {
  261. int ret;
  262. pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
  263. if (pdata) {
  264. switch (pdata->reset_gpio) {
  265. case 95:
  266. case 113:
  267. reset_gpio = pdata->reset_gpio;
  268. break;
  269. case 0:
  270. reset_gpio = 113;
  271. break;
  272. case -1:
  273. break;
  274. default:
  275. dev_err(&dev->dev, "Invalid reset GPIO %d\n",
  276. pdata->reset_gpio);
  277. }
  278. } else {
  279. if (cpu_is_pxa27x())
  280. reset_gpio = 113;
  281. }
  282. if (cpu_is_pxa27x()) {
  283. /*
  284. * This gpio is needed for a work-around to a bug in the ac97
  285. * controller during warm reset. The direction and level is set
  286. * here so that it is an output driven high when switching from
  287. * AC97_nRESET alt function to generic gpio.
  288. */
  289. ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
  290. "pxa27x ac97 reset");
  291. if (ret < 0) {
  292. pr_err("%s: gpio_request_one() failed: %d\n",
  293. __func__, ret);
  294. goto err_conf;
  295. }
  296. pxa27x_configure_ac97reset(reset_gpio, false);
  297. ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
  298. if (IS_ERR(ac97conf_clk)) {
  299. ret = PTR_ERR(ac97conf_clk);
  300. ac97conf_clk = NULL;
  301. goto err_conf;
  302. }
  303. }
  304. ac97_clk = clk_get(&dev->dev, "AC97CLK");
  305. if (IS_ERR(ac97_clk)) {
  306. ret = PTR_ERR(ac97_clk);
  307. ac97_clk = NULL;
  308. goto err_clk;
  309. }
  310. ret = clk_prepare_enable(ac97_clk);
  311. if (ret)
  312. goto err_clk2;
  313. ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
  314. if (ret < 0)
  315. goto err_irq;
  316. return 0;
  317. err_irq:
  318. GCR |= GCR_ACLINK_OFF;
  319. err_clk2:
  320. clk_put(ac97_clk);
  321. ac97_clk = NULL;
  322. err_clk:
  323. if (ac97conf_clk) {
  324. clk_put(ac97conf_clk);
  325. ac97conf_clk = NULL;
  326. }
  327. err_conf:
  328. return ret;
  329. }
  330. EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
  331. void pxa2xx_ac97_hw_remove(struct platform_device *dev)
  332. {
  333. if (cpu_is_pxa27x())
  334. gpio_free(reset_gpio);
  335. GCR |= GCR_ACLINK_OFF;
  336. free_irq(IRQ_AC97, NULL);
  337. if (ac97conf_clk) {
  338. clk_put(ac97conf_clk);
  339. ac97conf_clk = NULL;
  340. }
  341. clk_disable_unprepare(ac97_clk);
  342. clk_put(ac97_clk);
  343. ac97_clk = NULL;
  344. }
  345. EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
  346. MODULE_AUTHOR("Nicolas Pitre");
  347. MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
  348. MODULE_LICENSE("GPL");