gus_dma.c 7.0 KB

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  1. /*
  2. * Routines for GF1 DMA control
  3. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  4. *
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #include <asm/dma.h>
  22. #include <linux/slab.h>
  23. #include <sound/core.h>
  24. #include <sound/gus.h>
  25. static void snd_gf1_dma_ack(struct snd_gus_card * gus)
  26. {
  27. unsigned long flags;
  28. spin_lock_irqsave(&gus->reg_lock, flags);
  29. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, 0x00);
  30. snd_gf1_look8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL);
  31. spin_unlock_irqrestore(&gus->reg_lock, flags);
  32. }
  33. static void snd_gf1_dma_program(struct snd_gus_card * gus,
  34. unsigned int addr,
  35. unsigned long buf_addr,
  36. unsigned int count,
  37. unsigned int cmd)
  38. {
  39. unsigned long flags;
  40. unsigned int address;
  41. unsigned char dma_cmd;
  42. unsigned int address_high;
  43. snd_printdd("dma_transfer: addr=0x%x, buf=0x%lx, count=0x%x\n",
  44. addr, buf_addr, count);
  45. if (gus->gf1.dma1 > 3) {
  46. if (gus->gf1.enh_mode) {
  47. address = addr >> 1;
  48. } else {
  49. if (addr & 0x1f) {
  50. snd_printd("snd_gf1_dma_transfer: unaligned address (0x%x)?\n", addr);
  51. return;
  52. }
  53. address = (addr & 0x000c0000) | ((addr & 0x0003ffff) >> 1);
  54. }
  55. } else {
  56. address = addr;
  57. }
  58. dma_cmd = SNDRV_GF1_DMA_ENABLE | (unsigned short) cmd;
  59. #if 0
  60. dma_cmd |= 0x08;
  61. #endif
  62. if (dma_cmd & SNDRV_GF1_DMA_16BIT) {
  63. count++;
  64. count &= ~1; /* align */
  65. }
  66. if (gus->gf1.dma1 > 3) {
  67. dma_cmd |= SNDRV_GF1_DMA_WIDTH16;
  68. count++;
  69. count &= ~1; /* align */
  70. }
  71. snd_gf1_dma_ack(gus);
  72. snd_dma_program(gus->gf1.dma1, buf_addr, count, dma_cmd & SNDRV_GF1_DMA_READ ? DMA_MODE_READ : DMA_MODE_WRITE);
  73. #if 0
  74. snd_printk(KERN_DEBUG "address = 0x%x, count = 0x%x, dma_cmd = 0x%x\n",
  75. address << 1, count, dma_cmd);
  76. #endif
  77. spin_lock_irqsave(&gus->reg_lock, flags);
  78. if (gus->gf1.enh_mode) {
  79. address_high = ((address >> 16) & 0x000000f0) | (address & 0x0000000f);
  80. snd_gf1_write16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW, (unsigned short) (address >> 4));
  81. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_HIGH, (unsigned char) address_high);
  82. } else
  83. snd_gf1_write16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW, (unsigned short) (address >> 4));
  84. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, dma_cmd);
  85. spin_unlock_irqrestore(&gus->reg_lock, flags);
  86. }
  87. static struct snd_gf1_dma_block *snd_gf1_dma_next_block(struct snd_gus_card * gus)
  88. {
  89. struct snd_gf1_dma_block *block;
  90. /* PCM block have bigger priority than synthesizer one */
  91. if (gus->gf1.dma_data_pcm) {
  92. block = gus->gf1.dma_data_pcm;
  93. if (gus->gf1.dma_data_pcm_last == block) {
  94. gus->gf1.dma_data_pcm =
  95. gus->gf1.dma_data_pcm_last = NULL;
  96. } else {
  97. gus->gf1.dma_data_pcm = block->next;
  98. }
  99. } else if (gus->gf1.dma_data_synth) {
  100. block = gus->gf1.dma_data_synth;
  101. if (gus->gf1.dma_data_synth_last == block) {
  102. gus->gf1.dma_data_synth =
  103. gus->gf1.dma_data_synth_last = NULL;
  104. } else {
  105. gus->gf1.dma_data_synth = block->next;
  106. }
  107. } else {
  108. block = NULL;
  109. }
  110. if (block) {
  111. gus->gf1.dma_ack = block->ack;
  112. gus->gf1.dma_private_data = block->private_data;
  113. }
  114. return block;
  115. }
  116. static void snd_gf1_dma_interrupt(struct snd_gus_card * gus)
  117. {
  118. struct snd_gf1_dma_block *block;
  119. snd_gf1_dma_ack(gus);
  120. if (gus->gf1.dma_ack)
  121. gus->gf1.dma_ack(gus, gus->gf1.dma_private_data);
  122. spin_lock(&gus->dma_lock);
  123. if (gus->gf1.dma_data_pcm == NULL &&
  124. gus->gf1.dma_data_synth == NULL) {
  125. gus->gf1.dma_ack = NULL;
  126. gus->gf1.dma_flags &= ~SNDRV_GF1_DMA_TRIGGER;
  127. spin_unlock(&gus->dma_lock);
  128. return;
  129. }
  130. block = snd_gf1_dma_next_block(gus);
  131. spin_unlock(&gus->dma_lock);
  132. snd_gf1_dma_program(gus, block->addr, block->buf_addr, block->count, (unsigned short) block->cmd);
  133. kfree(block);
  134. #if 0
  135. snd_printd(KERN_DEBUG "program dma (IRQ) - "
  136. "addr = 0x%x, buffer = 0x%lx, count = 0x%x, cmd = 0x%x\n",
  137. block->addr, block->buf_addr, block->count, block->cmd);
  138. #endif
  139. }
  140. int snd_gf1_dma_init(struct snd_gus_card * gus)
  141. {
  142. mutex_lock(&gus->dma_mutex);
  143. gus->gf1.dma_shared++;
  144. if (gus->gf1.dma_shared > 1) {
  145. mutex_unlock(&gus->dma_mutex);
  146. return 0;
  147. }
  148. gus->gf1.interrupt_handler_dma_write = snd_gf1_dma_interrupt;
  149. gus->gf1.dma_data_pcm =
  150. gus->gf1.dma_data_pcm_last =
  151. gus->gf1.dma_data_synth =
  152. gus->gf1.dma_data_synth_last = NULL;
  153. mutex_unlock(&gus->dma_mutex);
  154. return 0;
  155. }
  156. int snd_gf1_dma_done(struct snd_gus_card * gus)
  157. {
  158. struct snd_gf1_dma_block *block;
  159. mutex_lock(&gus->dma_mutex);
  160. gus->gf1.dma_shared--;
  161. if (!gus->gf1.dma_shared) {
  162. snd_dma_disable(gus->gf1.dma1);
  163. snd_gf1_set_default_handlers(gus, SNDRV_GF1_HANDLER_DMA_WRITE);
  164. snd_gf1_dma_ack(gus);
  165. while ((block = gus->gf1.dma_data_pcm)) {
  166. gus->gf1.dma_data_pcm = block->next;
  167. kfree(block);
  168. }
  169. while ((block = gus->gf1.dma_data_synth)) {
  170. gus->gf1.dma_data_synth = block->next;
  171. kfree(block);
  172. }
  173. gus->gf1.dma_data_pcm_last =
  174. gus->gf1.dma_data_synth_last = NULL;
  175. }
  176. mutex_unlock(&gus->dma_mutex);
  177. return 0;
  178. }
  179. int snd_gf1_dma_transfer_block(struct snd_gus_card * gus,
  180. struct snd_gf1_dma_block * __block,
  181. int atomic,
  182. int synth)
  183. {
  184. unsigned long flags;
  185. struct snd_gf1_dma_block *block;
  186. block = kmalloc(sizeof(*block), atomic ? GFP_ATOMIC : GFP_KERNEL);
  187. if (block == NULL) {
  188. snd_printk(KERN_ERR "gf1: DMA transfer failure; not enough memory\n");
  189. return -ENOMEM;
  190. }
  191. *block = *__block;
  192. block->next = NULL;
  193. snd_printdd("addr = 0x%x, buffer = 0x%lx, count = 0x%x, cmd = 0x%x\n",
  194. block->addr, (long) block->buffer, block->count,
  195. block->cmd);
  196. snd_printdd("gus->gf1.dma_data_pcm_last = 0x%lx\n",
  197. (long)gus->gf1.dma_data_pcm_last);
  198. snd_printdd("gus->gf1.dma_data_pcm = 0x%lx\n",
  199. (long)gus->gf1.dma_data_pcm);
  200. spin_lock_irqsave(&gus->dma_lock, flags);
  201. if (synth) {
  202. if (gus->gf1.dma_data_synth_last) {
  203. gus->gf1.dma_data_synth_last->next = block;
  204. gus->gf1.dma_data_synth_last = block;
  205. } else {
  206. gus->gf1.dma_data_synth =
  207. gus->gf1.dma_data_synth_last = block;
  208. }
  209. } else {
  210. if (gus->gf1.dma_data_pcm_last) {
  211. gus->gf1.dma_data_pcm_last->next = block;
  212. gus->gf1.dma_data_pcm_last = block;
  213. } else {
  214. gus->gf1.dma_data_pcm =
  215. gus->gf1.dma_data_pcm_last = block;
  216. }
  217. }
  218. if (!(gus->gf1.dma_flags & SNDRV_GF1_DMA_TRIGGER)) {
  219. gus->gf1.dma_flags |= SNDRV_GF1_DMA_TRIGGER;
  220. block = snd_gf1_dma_next_block(gus);
  221. spin_unlock_irqrestore(&gus->dma_lock, flags);
  222. if (block == NULL)
  223. return 0;
  224. snd_gf1_dma_program(gus, block->addr, block->buf_addr, block->count, (unsigned short) block->cmd);
  225. kfree(block);
  226. return 0;
  227. }
  228. spin_unlock_irqrestore(&gus->dma_lock, flags);
  229. return 0;
  230. }