hal2.h 8.2 KB

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  1. #ifndef __HAL2_H
  2. #define __HAL2_H
  3. /*
  4. * Driver for HAL2 sound processors
  5. * Copyright (c) 1999 Ulf Carlsson <ulfc@bun.falkenberg.se>
  6. * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. *
  21. */
  22. #include <linux/types.h>
  23. /* Indirect status register */
  24. #define H2_ISR_TSTATUS 0x01 /* RO: transaction status 1=busy */
  25. #define H2_ISR_USTATUS 0x02 /* RO: utime status bit 1=armed */
  26. #define H2_ISR_QUAD_MODE 0x04 /* codec mode 0=indigo 1=quad */
  27. #define H2_ISR_GLOBAL_RESET_N 0x08 /* chip global reset 0=reset */
  28. #define H2_ISR_CODEC_RESET_N 0x10 /* codec/synth reset 0=reset */
  29. /* Revision register */
  30. #define H2_REV_AUDIO_PRESENT 0x8000 /* RO: audio present 0=present */
  31. #define H2_REV_BOARD_M 0x7000 /* RO: bits 14:12, board revision */
  32. #define H2_REV_MAJOR_CHIP_M 0x00F0 /* RO: bits 7:4, major chip revision */
  33. #define H2_REV_MINOR_CHIP_M 0x000F /* RO: bits 3:0, minor chip revision */
  34. /* Indirect address register */
  35. /*
  36. * Address of indirect internal register to be accessed. A write to this
  37. * register initiates read or write access to the indirect registers in the
  38. * HAL2. Note that there af four indirect data registers for write access to
  39. * registers larger than 16 byte.
  40. */
  41. #define H2_IAR_TYPE_M 0xF000 /* bits 15:12, type of functional */
  42. /* block the register resides in */
  43. /* 1=DMA Port */
  44. /* 9=Global DMA Control */
  45. /* 2=Bresenham */
  46. /* 3=Unix Timer */
  47. #define H2_IAR_NUM_M 0x0F00 /* bits 11:8 instance of the */
  48. /* blockin which the indirect */
  49. /* register resides */
  50. /* If IAR_TYPE_M=DMA Port: */
  51. /* 1=Synth In */
  52. /* 2=AES In */
  53. /* 3=AES Out */
  54. /* 4=DAC Out */
  55. /* 5=ADC Out */
  56. /* 6=Synth Control */
  57. /* If IAR_TYPE_M=Global DMA Control: */
  58. /* 1=Control */
  59. /* If IAR_TYPE_M=Bresenham: */
  60. /* 1=Bresenham Clock Gen 1 */
  61. /* 2=Bresenham Clock Gen 2 */
  62. /* 3=Bresenham Clock Gen 3 */
  63. /* If IAR_TYPE_M=Unix Timer: */
  64. /* 1=Unix Timer */
  65. #define H2_IAR_ACCESS_SELECT 0x0080 /* 1=read 0=write */
  66. #define H2_IAR_PARAM 0x000C /* Parameter Select */
  67. #define H2_IAR_RB_INDEX_M 0x0003 /* Read Back Index */
  68. /* 00:word0 */
  69. /* 01:word1 */
  70. /* 10:word2 */
  71. /* 11:word3 */
  72. /*
  73. * HAL2 internal addressing
  74. *
  75. * The HAL2 has "indirect registers" (idr) which are accessed by writing to the
  76. * Indirect Data registers. Write the address to the Indirect Address register
  77. * to transfer the data.
  78. *
  79. * We define the H2IR_* to the read address and H2IW_* to the write address and
  80. * H2I_* to be fields in whatever register is referred to.
  81. *
  82. * When we write to indirect registers which are larger than one word (16 bit)
  83. * we have to fill more than one indirect register before writing. When we read
  84. * back however we have to read several times, each time with different Read
  85. * Back Indexes (there are defs for doing this easily).
  86. */
  87. /*
  88. * Relay Control
  89. */
  90. #define H2I_RELAY_C 0x9100
  91. #define H2I_RELAY_C_STATE 0x01 /* state of RELAY pin signal */
  92. /* DMA port enable */
  93. #define H2I_DMA_PORT_EN 0x9104
  94. #define H2I_DMA_PORT_EN_SY_IN 0x01 /* Synth_in DMA port */
  95. #define H2I_DMA_PORT_EN_AESRX 0x02 /* AES receiver DMA port */
  96. #define H2I_DMA_PORT_EN_AESTX 0x04 /* AES transmitter DMA port */
  97. #define H2I_DMA_PORT_EN_CODECTX 0x08 /* CODEC transmit DMA port */
  98. #define H2I_DMA_PORT_EN_CODECR 0x10 /* CODEC receive DMA port */
  99. #define H2I_DMA_END 0x9108 /* global dma endian select */
  100. #define H2I_DMA_END_SY_IN 0x01 /* Synth_in DMA port */
  101. #define H2I_DMA_END_AESRX 0x02 /* AES receiver DMA port */
  102. #define H2I_DMA_END_AESTX 0x04 /* AES transmitter DMA port */
  103. #define H2I_DMA_END_CODECTX 0x08 /* CODEC transmit DMA port */
  104. #define H2I_DMA_END_CODECR 0x10 /* CODEC receive DMA port */
  105. /* 0=b_end 1=l_end */
  106. #define H2I_DMA_DRV 0x910C /* global PBUS DMA enable */
  107. #define H2I_SYNTH_C 0x1104 /* Synth DMA control */
  108. #define H2I_AESRX_C 0x1204 /* AES RX dma control */
  109. #define H2I_C_TS_EN 0x20 /* Timestamp enable */
  110. #define H2I_C_TS_FRMT 0x40 /* Timestamp format */
  111. #define H2I_C_NAUDIO 0x80 /* Sign extend */
  112. /* AESRX CTL, 16 bit */
  113. #define H2I_AESTX_C 0x1304 /* AES TX DMA control */
  114. #define H2I_AESTX_C_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
  115. #define H2I_AESTX_C_CLKID_M 0x18
  116. #define H2I_AESTX_C_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */
  117. #define H2I_AESTX_C_DATAT_M 0x300
  118. /* CODEC registers */
  119. #define H2I_DAC_C1 0x1404 /* DAC DMA control, 16 bit */
  120. #define H2I_DAC_C2 0x1408 /* DAC DMA control, 32 bit */
  121. #define H2I_ADC_C1 0x1504 /* ADC DMA control, 16 bit */
  122. #define H2I_ADC_C2 0x1508 /* ADC DMA control, 32 bit */
  123. /* Bits in CTL1 register */
  124. #define H2I_C1_DMA_SHIFT 0 /* DMA channel */
  125. #define H2I_C1_DMA_M 0x7
  126. #define H2I_C1_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
  127. #define H2I_C1_CLKID_M 0x18
  128. #define H2I_C1_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */
  129. #define H2I_C1_DATAT_M 0x300
  130. /* Bits in CTL2 register */
  131. #define H2I_C2_R_GAIN_SHIFT 0 /* right a/d input gain */
  132. #define H2I_C2_R_GAIN_M 0xf
  133. #define H2I_C2_L_GAIN_SHIFT 4 /* left a/d input gain */
  134. #define H2I_C2_L_GAIN_M 0xf0
  135. #define H2I_C2_R_SEL 0x100 /* right input select */
  136. #define H2I_C2_L_SEL 0x200 /* left input select */
  137. #define H2I_C2_MUTE 0x400 /* mute */
  138. #define H2I_C2_DO1 0x00010000 /* digital output port bit 0 */
  139. #define H2I_C2_DO2 0x00020000 /* digital output port bit 1 */
  140. #define H2I_C2_R_ATT_SHIFT 18 /* right d/a output - */
  141. #define H2I_C2_R_ATT_M 0x007c0000 /* attenuation */
  142. #define H2I_C2_L_ATT_SHIFT 23 /* left d/a output - */
  143. #define H2I_C2_L_ATT_M 0x0f800000 /* attenuation */
  144. #define H2I_SYNTH_MAP_C 0x1104 /* synth dma handshake ctrl */
  145. /* Clock generator CTL 1, 16 bit */
  146. #define H2I_BRES1_C1 0x2104
  147. #define H2I_BRES2_C1 0x2204
  148. #define H2I_BRES3_C1 0x2304
  149. #define H2I_BRES_C1_SHIFT 0 /* 0=48.0 1=44.1 2=aes_rx */
  150. #define H2I_BRES_C1_M 0x03
  151. /* Clock generator CTL 2, 32 bit */
  152. #define H2I_BRES1_C2 0x2108
  153. #define H2I_BRES2_C2 0x2208
  154. #define H2I_BRES3_C2 0x2308
  155. #define H2I_BRES_C2_INC_SHIFT 0 /* increment value */
  156. #define H2I_BRES_C2_INC_M 0xffff
  157. #define H2I_BRES_C2_MOD_SHIFT 16 /* modcontrol value */
  158. #define H2I_BRES_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */
  159. /* Unix timer, 64 bit */
  160. #define H2I_UTIME 0x3104
  161. #define H2I_UTIME_0_LD 0xffff /* microseconds, LSB's */
  162. #define H2I_UTIME_1_LD0 0x0f /* microseconds, MSB's */
  163. #define H2I_UTIME_1_LD1 0xf0 /* tenths of microseconds */
  164. #define H2I_UTIME_2_LD 0xffff /* seconds, LSB's */
  165. #define H2I_UTIME_3_LD 0xffff /* seconds, MSB's */
  166. struct hal2_ctl_regs {
  167. u32 _unused0[4];
  168. u32 isr; /* 0x10 Status Register */
  169. u32 _unused1[3];
  170. u32 rev; /* 0x20 Revision Register */
  171. u32 _unused2[3];
  172. u32 iar; /* 0x30 Indirect Address Register */
  173. u32 _unused3[3];
  174. u32 idr0; /* 0x40 Indirect Data Register 0 */
  175. u32 _unused4[3];
  176. u32 idr1; /* 0x50 Indirect Data Register 1 */
  177. u32 _unused5[3];
  178. u32 idr2; /* 0x60 Indirect Data Register 2 */
  179. u32 _unused6[3];
  180. u32 idr3; /* 0x70 Indirect Data Register 3 */
  181. };
  182. struct hal2_aes_regs {
  183. u32 rx_stat[2]; /* Status registers */
  184. u32 rx_cr[2]; /* Control registers */
  185. u32 rx_ud[4]; /* User data window */
  186. u32 rx_st[24]; /* Channel status data */
  187. u32 tx_stat[1]; /* Status register */
  188. u32 tx_cr[3]; /* Control registers */
  189. u32 tx_ud[4]; /* User data window */
  190. u32 tx_st[24]; /* Channel status data */
  191. };
  192. struct hal2_vol_regs {
  193. u32 right; /* Right volume */
  194. u32 left; /* Left volume */
  195. };
  196. struct hal2_syn_regs {
  197. u32 _unused0[2];
  198. u32 page; /* DOC Page register */
  199. u32 regsel; /* DOC Register selection */
  200. u32 dlow; /* DOC Data low */
  201. u32 dhigh; /* DOC Data high */
  202. u32 irq; /* IRQ Status */
  203. u32 dram; /* DRAM Access */
  204. };
  205. #endif /* __HAL2_H */