pcxhr_core.h 7.0 KB

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  1. /*
  2. * Driver for Digigram pcxhr compatible soundcards
  3. *
  4. * low level interface with interrupt and message handling
  5. *
  6. * Copyright (c) 2004 by Digigram <alsa@digigram.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #ifndef __SOUND_PCXHR_CORE_H
  23. #define __SOUND_PCXHR_CORE_H
  24. struct firmware;
  25. struct pcxhr_mgr;
  26. /* init and firmware download commands */
  27. void pcxhr_reset_xilinx_com(struct pcxhr_mgr *mgr);
  28. void pcxhr_reset_dsp(struct pcxhr_mgr *mgr);
  29. void pcxhr_enable_dsp(struct pcxhr_mgr *mgr);
  30. int pcxhr_load_xilinx_binary(struct pcxhr_mgr *mgr, const struct firmware *xilinx, int second);
  31. int pcxhr_load_eeprom_binary(struct pcxhr_mgr *mgr, const struct firmware *eeprom);
  32. int pcxhr_load_boot_binary(struct pcxhr_mgr *mgr, const struct firmware *boot);
  33. int pcxhr_load_dsp_binary(struct pcxhr_mgr *mgr, const struct firmware *dsp);
  34. /* DSP time available on MailBox4 register : 24 bit time samples() */
  35. #define PCXHR_DSP_TIME_MASK 0x00ffffff
  36. #define PCXHR_DSP_TIME_INVALID 0x10000000
  37. #define PCXHR_SIZE_MAX_CMD 8
  38. #define PCXHR_SIZE_MAX_STATUS 16
  39. #define PCXHR_SIZE_MAX_LONG_STATUS 256
  40. struct pcxhr_rmh {
  41. u16 cmd_len; /* length of the command to send (WORDs) */
  42. u16 stat_len; /* length of the status received (WORDs) */
  43. u16 dsp_stat; /* status type, RMP_SSIZE_XXX */
  44. u16 cmd_idx; /* index of the command */
  45. u32 cmd[PCXHR_SIZE_MAX_CMD];
  46. u32 stat[PCXHR_SIZE_MAX_STATUS];
  47. };
  48. enum {
  49. CMD_VERSION, /* cmd_len = 2 stat_len = 1 */
  50. CMD_SUPPORTED, /* cmd_len = 1 stat_len = 4 */
  51. CMD_TEST_IT, /* cmd_len = 1 stat_len = 1 */
  52. CMD_SEND_IRQA, /* cmd_len = 1 stat_len = 0 */
  53. CMD_ACCESS_IO_WRITE, /* cmd_len >= 1 stat_len >= 1 */
  54. CMD_ACCESS_IO_READ, /* cmd_len >= 1 stat_len >= 1 */
  55. CMD_ASYNC, /* cmd_len = 1 stat_len = 1 */
  56. CMD_MODIFY_CLOCK, /* cmd_len = 3 stat_len = 0 */
  57. CMD_RESYNC_AUDIO_INPUTS, /* cmd_len = 1 stat_len = 0 */
  58. CMD_GET_DSP_RESOURCES, /* cmd_len = 1 stat_len = 4 */
  59. CMD_SET_TIMER_INTERRUPT, /* cmd_len = 1 stat_len = 0 */
  60. CMD_RES_PIPE, /* cmd_len >=2 stat_len = 0 */
  61. CMD_FREE_PIPE, /* cmd_len = 1 stat_len = 0 */
  62. CMD_CONF_PIPE, /* cmd_len = 2 stat_len = 0 */
  63. CMD_STOP_PIPE, /* cmd_len = 1 stat_len = 0 */
  64. CMD_PIPE_SAMPLE_COUNT, /* cmd_len = 2 stat_len = 2 */
  65. CMD_CAN_START_PIPE, /* cmd_len >= 1 stat_len = 1 */
  66. CMD_START_STREAM, /* cmd_len = 2 stat_len = 0 */
  67. CMD_STREAM_OUT_LEVEL_ADJUST, /* cmd_len >= 1 stat_len = 0 */
  68. CMD_STOP_STREAM, /* cmd_len = 2 stat_len = 0 */
  69. CMD_UPDATE_R_BUFFERS, /* cmd_len = 4 stat_len = 0 */
  70. CMD_FORMAT_STREAM_OUT, /* cmd_len >= 2 stat_len = 0 */
  71. CMD_FORMAT_STREAM_IN, /* cmd_len >= 4 stat_len = 0 */
  72. CMD_STREAM_SAMPLE_COUNT, /* cmd_len = 2 stat_len = (2 * nb_stream) */
  73. CMD_AUDIO_LEVEL_ADJUST, /* cmd_len = 3 stat_len = 0 */
  74. CMD_GET_TIME_CODE, /* cmd_len = 1 stat_len = 5 */
  75. CMD_MANAGE_SIGNAL, /* cmd_len = 1 stat_len = 0 */
  76. CMD_LAST_INDEX
  77. };
  78. #define MASK_DSP_WORD 0x00ffffff
  79. #define MASK_ALL_STREAM 0x00ffffff
  80. #define MASK_DSP_WORD_LEVEL 0x000001ff
  81. #define MASK_FIRST_FIELD 0x0000001f
  82. #define FIELD_SIZE 5
  83. /*
  84. init the rmh struct; by default cmd_len is set to 1
  85. */
  86. void pcxhr_init_rmh(struct pcxhr_rmh *rmh, int cmd);
  87. void pcxhr_set_pipe_cmd_params(struct pcxhr_rmh* rmh, int capture, unsigned int param1,
  88. unsigned int param2, unsigned int param3);
  89. #define DSP_EXT_CMD_SET(x) (x->dsp_version > 0x012800)
  90. /*
  91. send the rmh
  92. */
  93. int pcxhr_send_msg(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh);
  94. /* values used for CMD_ACCESS_IO_WRITE and CMD_ACCESS_IO_READ */
  95. #define IO_NUM_REG_CONT 0
  96. #define IO_NUM_REG_GENCLK 1
  97. #define IO_NUM_REG_MUTE_OUT 2
  98. #define IO_NUM_SPEED_RATIO 4
  99. #define IO_NUM_REG_STATUS 5
  100. #define IO_NUM_REG_CUER 10
  101. #define IO_NUM_UER_CHIP_REG 11
  102. #define IO_NUM_REG_CONFIG_SRC 12
  103. #define IO_NUM_REG_OUT_ANA_LEVEL 20
  104. #define IO_NUM_REG_IN_ANA_LEVEL 21
  105. #define REG_CONT_VALSMPTE 0x000800
  106. #define REG_CONT_UNMUTE_INPUTS 0x020000
  107. /* parameters used with register IO_NUM_REG_STATUS */
  108. #define REG_STATUS_OPTIONS 0
  109. #define REG_STATUS_AES_SYNC 8
  110. #define REG_STATUS_AES_1 9
  111. #define REG_STATUS_AES_2 10
  112. #define REG_STATUS_AES_3 11
  113. #define REG_STATUS_AES_4 12
  114. #define REG_STATUS_WORD_CLOCK 13
  115. #define REG_STATUS_INTER_SYNC 14
  116. #define REG_STATUS_CURRENT 0x80
  117. /* results */
  118. #define REG_STATUS_OPT_NO_VIDEO_SIGNAL 0x01
  119. #define REG_STATUS_OPT_DAUGHTER_MASK 0x1c
  120. #define REG_STATUS_OPT_ANALOG_BOARD 0x00
  121. #define REG_STATUS_OPT_NO_DAUGHTER 0x1c
  122. #define REG_STATUS_OPT_COMPANION_MASK 0xe0
  123. #define REG_STATUS_OPT_NO_COMPANION 0xe0
  124. #define REG_STATUS_SYNC_32000 0x00
  125. #define REG_STATUS_SYNC_44100 0x01
  126. #define REG_STATUS_SYNC_48000 0x02
  127. #define REG_STATUS_SYNC_64000 0x03
  128. #define REG_STATUS_SYNC_88200 0x04
  129. #define REG_STATUS_SYNC_96000 0x05
  130. #define REG_STATUS_SYNC_128000 0x06
  131. #define REG_STATUS_SYNC_176400 0x07
  132. #define REG_STATUS_SYNC_192000 0x08
  133. int pcxhr_set_pipe_state(struct pcxhr_mgr *mgr, int playback_mask, int capture_mask, int start);
  134. int pcxhr_write_io_num_reg_cont(struct pcxhr_mgr *mgr, unsigned int mask,
  135. unsigned int value, int *changed);
  136. /* codec parameters */
  137. #define CS8416_RUN 0x200401
  138. #define CS8416_FORMAT_DETECT 0x200b00
  139. #define CS8416_CSB0 0x201900
  140. #define CS8416_CSB1 0x201a00
  141. #define CS8416_CSB2 0x201b00
  142. #define CS8416_CSB3 0x201c00
  143. #define CS8416_CSB4 0x201d00
  144. #define CS8416_VERSION 0x207f00
  145. #define CS8420_DATA_FLOW_CTL 0x200301
  146. #define CS8420_CLOCK_SRC_CTL 0x200401
  147. #define CS8420_RECEIVER_ERRORS 0x201000
  148. #define CS8420_SRC_RATIO 0x201e00
  149. #define CS8420_CSB0 0x202000
  150. #define CS8420_CSB1 0x202100
  151. #define CS8420_CSB2 0x202200
  152. #define CS8420_CSB3 0x202300
  153. #define CS8420_CSB4 0x202400
  154. #define CS8420_VERSION 0x207f00
  155. #define CS4271_MODE_CTL_1 0x200101
  156. #define CS4271_DAC_CTL 0x200201
  157. #define CS4271_VOLMIX 0x200301
  158. #define CS4271_VOLMUTE_LEFT 0x200401
  159. #define CS4271_VOLMUTE_RIGHT 0x200501
  160. #define CS4271_ADC_CTL 0x200601
  161. #define CS4271_MODE_CTL_2 0x200701
  162. #define CHIP_SIG_AND_MAP_SPI 0xff7f00
  163. /* codec selection */
  164. #define CS4271_01_CS 0x160018
  165. #define CS4271_23_CS 0x160019
  166. #define CS4271_45_CS 0x16001a
  167. #define CS4271_67_CS 0x16001b
  168. #define CS4271_89_CS 0x16001c
  169. #define CS4271_AB_CS 0x16001d
  170. #define CS8420_01_CS 0x080090
  171. #define CS8420_23_CS 0x080092
  172. #define CS8420_45_CS 0x080094
  173. #define CS8420_67_CS 0x080096
  174. #define CS8416_01_CS 0x080098
  175. /* interrupt handling */
  176. irqreturn_t pcxhr_interrupt(int irq, void *dev_id);
  177. irqreturn_t pcxhr_threaded_irq(int irq, void *dev_id);
  178. #endif /* __SOUND_PCXHR_CORE_H */