imx-ssi.h 6.2 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License version 2 as
  4. * published by the Free Software Foundation.
  5. */
  6. #ifndef _IMX_SSI_H
  7. #define _IMX_SSI_H
  8. #define SSI_STX0 0x00
  9. #define SSI_STX1 0x04
  10. #define SSI_SRX0 0x08
  11. #define SSI_SRX1 0x0c
  12. #define SSI_SCR 0x10
  13. #define SSI_SCR_CLK_IST (1 << 9)
  14. #define SSI_SCR_CLK_IST_SHIFT 9
  15. #define SSI_SCR_TCH_EN (1 << 8)
  16. #define SSI_SCR_SYS_CLK_EN (1 << 7)
  17. #define SSI_SCR_I2S_MODE_NORM (0 << 5)
  18. #define SSI_SCR_I2S_MODE_MSTR (1 << 5)
  19. #define SSI_SCR_I2S_MODE_SLAVE (2 << 5)
  20. #define SSI_I2S_MODE_MASK (3 << 5)
  21. #define SSI_SCR_SYN (1 << 4)
  22. #define SSI_SCR_NET (1 << 3)
  23. #define SSI_SCR_RE (1 << 2)
  24. #define SSI_SCR_TE (1 << 1)
  25. #define SSI_SCR_SSIEN (1 << 0)
  26. #define SSI_SISR 0x14
  27. #define SSI_SISR_MASK ((1 << 19) - 1)
  28. #define SSI_SISR_CMDAU (1 << 18)
  29. #define SSI_SISR_CMDDU (1 << 17)
  30. #define SSI_SISR_RXT (1 << 16)
  31. #define SSI_SISR_RDR1 (1 << 15)
  32. #define SSI_SISR_RDR0 (1 << 14)
  33. #define SSI_SISR_TDE1 (1 << 13)
  34. #define SSI_SISR_TDE0 (1 << 12)
  35. #define SSI_SISR_ROE1 (1 << 11)
  36. #define SSI_SISR_ROE0 (1 << 10)
  37. #define SSI_SISR_TUE1 (1 << 9)
  38. #define SSI_SISR_TUE0 (1 << 8)
  39. #define SSI_SISR_TFS (1 << 7)
  40. #define SSI_SISR_RFS (1 << 6)
  41. #define SSI_SISR_TLS (1 << 5)
  42. #define SSI_SISR_RLS (1 << 4)
  43. #define SSI_SISR_RFF1 (1 << 3)
  44. #define SSI_SISR_RFF0 (1 << 2)
  45. #define SSI_SISR_TFE1 (1 << 1)
  46. #define SSI_SISR_TFE0 (1 << 0)
  47. #define SSI_SIER 0x18
  48. #define SSI_SIER_RDMAE (1 << 22)
  49. #define SSI_SIER_RIE (1 << 21)
  50. #define SSI_SIER_TDMAE (1 << 20)
  51. #define SSI_SIER_TIE (1 << 19)
  52. #define SSI_SIER_CMDAU_EN (1 << 18)
  53. #define SSI_SIER_CMDDU_EN (1 << 17)
  54. #define SSI_SIER_RXT_EN (1 << 16)
  55. #define SSI_SIER_RDR1_EN (1 << 15)
  56. #define SSI_SIER_RDR0_EN (1 << 14)
  57. #define SSI_SIER_TDE1_EN (1 << 13)
  58. #define SSI_SIER_TDE0_EN (1 << 12)
  59. #define SSI_SIER_ROE1_EN (1 << 11)
  60. #define SSI_SIER_ROE0_EN (1 << 10)
  61. #define SSI_SIER_TUE1_EN (1 << 9)
  62. #define SSI_SIER_TUE0_EN (1 << 8)
  63. #define SSI_SIER_TFS_EN (1 << 7)
  64. #define SSI_SIER_RFS_EN (1 << 6)
  65. #define SSI_SIER_TLS_EN (1 << 5)
  66. #define SSI_SIER_RLS_EN (1 << 4)
  67. #define SSI_SIER_RFF1_EN (1 << 3)
  68. #define SSI_SIER_RFF0_EN (1 << 2)
  69. #define SSI_SIER_TFE1_EN (1 << 1)
  70. #define SSI_SIER_TFE0_EN (1 << 0)
  71. #define SSI_STCR 0x1c
  72. #define SSI_STCR_TXBIT0 (1 << 9)
  73. #define SSI_STCR_TFEN1 (1 << 8)
  74. #define SSI_STCR_TFEN0 (1 << 7)
  75. #define SSI_FIFO_ENABLE_0_SHIFT 7
  76. #define SSI_STCR_TFDIR (1 << 6)
  77. #define SSI_STCR_TXDIR (1 << 5)
  78. #define SSI_STCR_TSHFD (1 << 4)
  79. #define SSI_STCR_TSCKP (1 << 3)
  80. #define SSI_STCR_TFSI (1 << 2)
  81. #define SSI_STCR_TFSL (1 << 1)
  82. #define SSI_STCR_TEFS (1 << 0)
  83. #define SSI_SRCR 0x20
  84. #define SSI_SRCR_RXBIT0 (1 << 9)
  85. #define SSI_SRCR_RFEN1 (1 << 8)
  86. #define SSI_SRCR_RFEN0 (1 << 7)
  87. #define SSI_FIFO_ENABLE_0_SHIFT 7
  88. #define SSI_SRCR_RFDIR (1 << 6)
  89. #define SSI_SRCR_RXDIR (1 << 5)
  90. #define SSI_SRCR_RSHFD (1 << 4)
  91. #define SSI_SRCR_RSCKP (1 << 3)
  92. #define SSI_SRCR_RFSI (1 << 2)
  93. #define SSI_SRCR_RFSL (1 << 1)
  94. #define SSI_SRCR_REFS (1 << 0)
  95. #define SSI_SRCCR 0x28
  96. #define SSI_SRCCR_DIV2 (1 << 18)
  97. #define SSI_SRCCR_PSR (1 << 17)
  98. #define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13)
  99. #define SSI_SRCCR_DC(x) (((x) & 0x1f) << 8)
  100. #define SSI_SRCCR_PM(x) (((x) & 0xff) << 0)
  101. #define SSI_SRCCR_WL_MASK (0xf << 13)
  102. #define SSI_SRCCR_DC_MASK (0x1f << 8)
  103. #define SSI_SRCCR_PM_MASK (0xff << 0)
  104. #define SSI_STCCR 0x24
  105. #define SSI_STCCR_DIV2 (1 << 18)
  106. #define SSI_STCCR_PSR (1 << 17)
  107. #define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13)
  108. #define SSI_STCCR_DC(x) (((x) & 0x1f) << 8)
  109. #define SSI_STCCR_PM(x) (((x) & 0xff) << 0)
  110. #define SSI_STCCR_WL_MASK (0xf << 13)
  111. #define SSI_STCCR_DC_MASK (0x1f << 8)
  112. #define SSI_STCCR_PM_MASK (0xff << 0)
  113. #define SSI_SFCSR 0x2c
  114. #define SSI_SFCSR_RFCNT1(x) (((x) & 0xf) << 28)
  115. #define SSI_RX_FIFO_1_COUNT_SHIFT 28
  116. #define SSI_SFCSR_TFCNT1(x) (((x) & 0xf) << 24)
  117. #define SSI_TX_FIFO_1_COUNT_SHIFT 24
  118. #define SSI_SFCSR_RFWM1(x) (((x) & 0xf) << 20)
  119. #define SSI_SFCSR_TFWM1(x) (((x) & 0xf) << 16)
  120. #define SSI_SFCSR_RFCNT0(x) (((x) & 0xf) << 12)
  121. #define SSI_RX_FIFO_0_COUNT_SHIFT 12
  122. #define SSI_SFCSR_TFCNT0(x) (((x) & 0xf) << 8)
  123. #define SSI_TX_FIFO_0_COUNT_SHIFT 8
  124. #define SSI_SFCSR_RFWM0(x) (((x) & 0xf) << 4)
  125. #define SSI_SFCSR_TFWM0(x) (((x) & 0xf) << 0)
  126. #define SSI_SFCSR_RFWM0_MASK (0xf << 4)
  127. #define SSI_SFCSR_TFWM0_MASK (0xf << 0)
  128. #define SSI_STR 0x30
  129. #define SSI_STR_TEST (1 << 15)
  130. #define SSI_STR_RCK2TCK (1 << 14)
  131. #define SSI_STR_RFS2TFS (1 << 13)
  132. #define SSI_STR_RXSTATE(x) (((x) & 0xf) << 8)
  133. #define SSI_STR_TXD2RXD (1 << 7)
  134. #define SSI_STR_TCK2RCK (1 << 6)
  135. #define SSI_STR_TFS2RFS (1 << 5)
  136. #define SSI_STR_TXSTATE(x) (((x) & 0xf) << 0)
  137. #define SSI_SOR 0x34
  138. #define SSI_SOR_CLKOFF (1 << 6)
  139. #define SSI_SOR_RX_CLR (1 << 5)
  140. #define SSI_SOR_TX_CLR (1 << 4)
  141. #define SSI_SOR_INIT (1 << 3)
  142. #define SSI_SOR_WAIT(x) (((x) & 0x3) << 1)
  143. #define SSI_SOR_WAIT_MASK (0x3 << 1)
  144. #define SSI_SOR_SYNRST (1 << 0)
  145. #define SSI_SACNT 0x38
  146. #define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5)
  147. #define SSI_SACNT_WR (1 << 4)
  148. #define SSI_SACNT_RD (1 << 3)
  149. #define SSI_SACNT_TIF (1 << 2)
  150. #define SSI_SACNT_FV (1 << 1)
  151. #define SSI_SACNT_AC97EN (1 << 0)
  152. #define SSI_SACADD 0x3c
  153. #define SSI_SACDAT 0x40
  154. #define SSI_SATAG 0x44
  155. #define SSI_STMSK 0x48
  156. #define SSI_SRMSK 0x4c
  157. #define SSI_SACCST 0x50
  158. #define SSI_SACCEN 0x54
  159. #define SSI_SACCDIS 0x58
  160. /* SSI clock sources */
  161. #define IMX_SSP_SYS_CLK 0
  162. /* SSI audio dividers */
  163. #define IMX_SSI_TX_DIV_2 0
  164. #define IMX_SSI_TX_DIV_PSR 1
  165. #define IMX_SSI_TX_DIV_PM 2
  166. #define IMX_SSI_RX_DIV_2 3
  167. #define IMX_SSI_RX_DIV_PSR 4
  168. #define IMX_SSI_RX_DIV_PM 5
  169. #define DRV_NAME "imx-ssi"
  170. #include <linux/dmaengine.h>
  171. #include <linux/platform_data/dma-imx.h>
  172. #include <sound/dmaengine_pcm.h>
  173. #include "imx-pcm.h"
  174. struct imx_ssi {
  175. struct platform_device *ac97_dev;
  176. struct snd_soc_dai *imx_ac97;
  177. struct clk *clk;
  178. void __iomem *base;
  179. int irq;
  180. int fiq_enable;
  181. unsigned int offset;
  182. unsigned int flags;
  183. void (*ac97_reset) (struct snd_ac97 *ac97);
  184. void (*ac97_warm_reset)(struct snd_ac97 *ac97);
  185. struct snd_dmaengine_dai_dma_data dma_params_rx;
  186. struct snd_dmaengine_dai_dma_data dma_params_tx;
  187. struct imx_dma_data filter_data_tx;
  188. struct imx_dma_data filter_data_rx;
  189. struct imx_pcm_fiq_params fiq_params;
  190. int fiq_init;
  191. int dma_init;
  192. };
  193. #endif /* _IMX_SSI_H */