omap-dmic.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531
  1. /*
  2. * omap-dmic.c -- OMAP ASoC DMIC DAI driver
  3. *
  4. * Copyright (C) 2010 - 2011 Texas Instruments
  5. *
  6. * Author: David Lambert <dlambert@ti.com>
  7. * Misael Lopez Cruz <misael.lopez@ti.com>
  8. * Liam Girdwood <lrg@ti.com>
  9. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * version 2 as published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23. * 02110-1301 USA
  24. *
  25. */
  26. #include <linux/init.h>
  27. #include <linux/module.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/err.h>
  30. #include <linux/clk.h>
  31. #include <linux/io.h>
  32. #include <linux/slab.h>
  33. #include <linux/pm_runtime.h>
  34. #include <linux/of_device.h>
  35. #include <sound/core.h>
  36. #include <sound/pcm.h>
  37. #include <sound/pcm_params.h>
  38. #include <sound/initval.h>
  39. #include <sound/soc.h>
  40. #include <sound/dmaengine_pcm.h>
  41. #include <sound/omap-pcm.h>
  42. #include "omap-dmic.h"
  43. struct omap_dmic {
  44. struct device *dev;
  45. void __iomem *io_base;
  46. struct clk *fclk;
  47. struct pm_qos_request pm_qos_req;
  48. int latency;
  49. int fclk_freq;
  50. int out_freq;
  51. int clk_div;
  52. int sysclk;
  53. int threshold;
  54. u32 ch_enabled;
  55. bool active;
  56. struct mutex mutex;
  57. struct snd_dmaengine_dai_dma_data dma_data;
  58. };
  59. static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
  60. {
  61. writel_relaxed(val, dmic->io_base + reg);
  62. }
  63. static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
  64. {
  65. return readl_relaxed(dmic->io_base + reg);
  66. }
  67. static inline void omap_dmic_start(struct omap_dmic *dmic)
  68. {
  69. u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  70. /* Configure DMA controller */
  71. omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
  72. OMAP_DMIC_DMA_ENABLE);
  73. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled);
  74. }
  75. static inline void omap_dmic_stop(struct omap_dmic *dmic)
  76. {
  77. u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  78. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
  79. ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);
  80. /* Disable DMA request generation */
  81. omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
  82. OMAP_DMIC_DMA_ENABLE);
  83. }
  84. static inline int dmic_is_enabled(struct omap_dmic *dmic)
  85. {
  86. return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
  87. OMAP_DMIC_UP_ENABLE_MASK;
  88. }
  89. static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
  90. struct snd_soc_dai *dai)
  91. {
  92. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  93. int ret = 0;
  94. mutex_lock(&dmic->mutex);
  95. if (!dai->active)
  96. dmic->active = 1;
  97. else
  98. ret = -EBUSY;
  99. mutex_unlock(&dmic->mutex);
  100. return ret;
  101. }
  102. static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
  103. struct snd_soc_dai *dai)
  104. {
  105. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  106. mutex_lock(&dmic->mutex);
  107. pm_qos_remove_request(&dmic->pm_qos_req);
  108. if (!dai->active)
  109. dmic->active = 0;
  110. mutex_unlock(&dmic->mutex);
  111. }
  112. static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
  113. {
  114. int divider = -EINVAL;
  115. /*
  116. * 192KHz rate is only supported with 19.2MHz/3.84MHz clock
  117. * configuration.
  118. */
  119. if (sample_rate == 192000) {
  120. if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
  121. divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
  122. else
  123. dev_err(dmic->dev,
  124. "invalid clock configuration for 192KHz\n");
  125. return divider;
  126. }
  127. switch (dmic->out_freq) {
  128. case 1536000:
  129. if (dmic->fclk_freq != 24576000)
  130. goto div_err;
  131. divider = 0x4; /* Divider: 16 */
  132. break;
  133. case 2400000:
  134. switch (dmic->fclk_freq) {
  135. case 12000000:
  136. divider = 0x5; /* Divider: 5 */
  137. break;
  138. case 19200000:
  139. divider = 0x0; /* Divider: 8 */
  140. break;
  141. case 24000000:
  142. divider = 0x2; /* Divider: 10 */
  143. break;
  144. default:
  145. goto div_err;
  146. }
  147. break;
  148. case 3072000:
  149. if (dmic->fclk_freq != 24576000)
  150. goto div_err;
  151. divider = 0x3; /* Divider: 8 */
  152. break;
  153. case 3840000:
  154. if (dmic->fclk_freq != 19200000)
  155. goto div_err;
  156. divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
  157. break;
  158. default:
  159. dev_err(dmic->dev, "invalid out frequency: %dHz\n",
  160. dmic->out_freq);
  161. break;
  162. }
  163. return divider;
  164. div_err:
  165. dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
  166. dmic->out_freq, dmic->fclk_freq);
  167. return -EINVAL;
  168. }
  169. static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
  170. struct snd_pcm_hw_params *params,
  171. struct snd_soc_dai *dai)
  172. {
  173. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  174. struct snd_dmaengine_dai_dma_data *dma_data;
  175. int channels;
  176. dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
  177. if (dmic->clk_div < 0) {
  178. dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
  179. dmic->out_freq, dmic->fclk_freq);
  180. return -EINVAL;
  181. }
  182. dmic->ch_enabled = 0;
  183. channels = params_channels(params);
  184. switch (channels) {
  185. case 6:
  186. dmic->ch_enabled |= OMAP_DMIC_UP3_ENABLE;
  187. case 4:
  188. dmic->ch_enabled |= OMAP_DMIC_UP2_ENABLE;
  189. case 2:
  190. dmic->ch_enabled |= OMAP_DMIC_UP1_ENABLE;
  191. break;
  192. default:
  193. dev_err(dmic->dev, "invalid number of legacy channels\n");
  194. return -EINVAL;
  195. }
  196. /* packet size is threshold * channels */
  197. dma_data = snd_soc_dai_get_dma_data(dai, substream);
  198. dma_data->maxburst = dmic->threshold * channels;
  199. dmic->latency = (OMAP_DMIC_THRES_MAX - dmic->threshold) * USEC_PER_SEC /
  200. params_rate(params);
  201. return 0;
  202. }
  203. static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
  204. struct snd_soc_dai *dai)
  205. {
  206. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  207. u32 ctrl;
  208. if (pm_qos_request_active(&dmic->pm_qos_req))
  209. pm_qos_update_request(&dmic->pm_qos_req, dmic->latency);
  210. /* Configure uplink threshold */
  211. omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);
  212. ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  213. /* Set dmic out format */
  214. ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK);
  215. ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
  216. OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
  217. /* Configure dmic clock divider */
  218. ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
  219. ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div);
  220. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);
  221. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
  222. ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
  223. OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
  224. return 0;
  225. }
  226. static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
  227. int cmd, struct snd_soc_dai *dai)
  228. {
  229. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  230. switch (cmd) {
  231. case SNDRV_PCM_TRIGGER_START:
  232. omap_dmic_start(dmic);
  233. break;
  234. case SNDRV_PCM_TRIGGER_STOP:
  235. omap_dmic_stop(dmic);
  236. break;
  237. default:
  238. break;
  239. }
  240. return 0;
  241. }
  242. static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
  243. unsigned int freq)
  244. {
  245. struct clk *parent_clk;
  246. char *parent_clk_name;
  247. int ret = 0;
  248. switch (freq) {
  249. case 12000000:
  250. case 19200000:
  251. case 24000000:
  252. case 24576000:
  253. break;
  254. default:
  255. dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
  256. dmic->fclk_freq = 0;
  257. return -EINVAL;
  258. }
  259. if (dmic->sysclk == clk_id) {
  260. dmic->fclk_freq = freq;
  261. return 0;
  262. }
  263. /* re-parent not allowed if a stream is ongoing */
  264. if (dmic->active && dmic_is_enabled(dmic)) {
  265. dev_err(dmic->dev, "can't re-parent when DMIC active\n");
  266. return -EBUSY;
  267. }
  268. switch (clk_id) {
  269. case OMAP_DMIC_SYSCLK_PAD_CLKS:
  270. parent_clk_name = "pad_clks_ck";
  271. break;
  272. case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
  273. parent_clk_name = "slimbus_clk";
  274. break;
  275. case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
  276. parent_clk_name = "dmic_sync_mux_ck";
  277. break;
  278. default:
  279. dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
  280. return -EINVAL;
  281. }
  282. parent_clk = clk_get(dmic->dev, parent_clk_name);
  283. if (IS_ERR(parent_clk)) {
  284. dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
  285. return -ENODEV;
  286. }
  287. mutex_lock(&dmic->mutex);
  288. if (dmic->active) {
  289. /* disable clock while reparenting */
  290. pm_runtime_put_sync(dmic->dev);
  291. ret = clk_set_parent(dmic->fclk, parent_clk);
  292. pm_runtime_get_sync(dmic->dev);
  293. } else {
  294. ret = clk_set_parent(dmic->fclk, parent_clk);
  295. }
  296. mutex_unlock(&dmic->mutex);
  297. if (ret < 0) {
  298. dev_err(dmic->dev, "re-parent failed\n");
  299. goto err_busy;
  300. }
  301. dmic->sysclk = clk_id;
  302. dmic->fclk_freq = freq;
  303. err_busy:
  304. clk_put(parent_clk);
  305. return ret;
  306. }
  307. static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
  308. unsigned int freq)
  309. {
  310. int ret = 0;
  311. if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
  312. dev_err(dmic->dev, "output clk_id (%d) not supported\n",
  313. clk_id);
  314. return -EINVAL;
  315. }
  316. switch (freq) {
  317. case 1536000:
  318. case 2400000:
  319. case 3072000:
  320. case 3840000:
  321. dmic->out_freq = freq;
  322. break;
  323. default:
  324. dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
  325. dmic->out_freq = 0;
  326. ret = -EINVAL;
  327. }
  328. return ret;
  329. }
  330. static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  331. unsigned int freq, int dir)
  332. {
  333. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  334. if (dir == SND_SOC_CLOCK_IN)
  335. return omap_dmic_select_fclk(dmic, clk_id, freq);
  336. else if (dir == SND_SOC_CLOCK_OUT)
  337. return omap_dmic_select_outclk(dmic, clk_id, freq);
  338. dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
  339. return -EINVAL;
  340. }
  341. static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
  342. .startup = omap_dmic_dai_startup,
  343. .shutdown = omap_dmic_dai_shutdown,
  344. .hw_params = omap_dmic_dai_hw_params,
  345. .prepare = omap_dmic_dai_prepare,
  346. .trigger = omap_dmic_dai_trigger,
  347. .set_sysclk = omap_dmic_set_dai_sysclk,
  348. };
  349. static int omap_dmic_probe(struct snd_soc_dai *dai)
  350. {
  351. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  352. pm_runtime_enable(dmic->dev);
  353. /* Disable lines while request is ongoing */
  354. pm_runtime_get_sync(dmic->dev);
  355. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
  356. pm_runtime_put_sync(dmic->dev);
  357. /* Configure DMIC threshold value */
  358. dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
  359. snd_soc_dai_init_dma_data(dai, NULL, &dmic->dma_data);
  360. return 0;
  361. }
  362. static int omap_dmic_remove(struct snd_soc_dai *dai)
  363. {
  364. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  365. pm_runtime_disable(dmic->dev);
  366. return 0;
  367. }
  368. static struct snd_soc_dai_driver omap_dmic_dai = {
  369. .name = "omap-dmic",
  370. .probe = omap_dmic_probe,
  371. .remove = omap_dmic_remove,
  372. .capture = {
  373. .channels_min = 2,
  374. .channels_max = 6,
  375. .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
  376. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  377. .sig_bits = 24,
  378. },
  379. .ops = &omap_dmic_dai_ops,
  380. };
  381. static const struct snd_soc_component_driver omap_dmic_component = {
  382. .name = "omap-dmic",
  383. };
  384. static int asoc_dmic_probe(struct platform_device *pdev)
  385. {
  386. struct omap_dmic *dmic;
  387. struct resource *res;
  388. int ret;
  389. dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
  390. if (!dmic)
  391. return -ENOMEM;
  392. platform_set_drvdata(pdev, dmic);
  393. dmic->dev = &pdev->dev;
  394. dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;
  395. mutex_init(&dmic->mutex);
  396. dmic->fclk = devm_clk_get(dmic->dev, "fck");
  397. if (IS_ERR(dmic->fclk)) {
  398. dev_err(dmic->dev, "cant get fck\n");
  399. return -ENODEV;
  400. }
  401. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  402. if (!res) {
  403. dev_err(dmic->dev, "invalid dma memory resource\n");
  404. return -ENODEV;
  405. }
  406. dmic->dma_data.addr = res->start + OMAP_DMIC_DATA_REG;
  407. dmic->dma_data.filter_data = "up_link";
  408. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  409. dmic->io_base = devm_ioremap_resource(&pdev->dev, res);
  410. if (IS_ERR(dmic->io_base))
  411. return PTR_ERR(dmic->io_base);
  412. ret = devm_snd_soc_register_component(&pdev->dev,
  413. &omap_dmic_component,
  414. &omap_dmic_dai, 1);
  415. if (ret)
  416. return ret;
  417. ret = omap_pcm_platform_register(&pdev->dev);
  418. if (ret)
  419. return ret;
  420. return 0;
  421. }
  422. static const struct of_device_id omap_dmic_of_match[] = {
  423. { .compatible = "ti,omap4-dmic", },
  424. { }
  425. };
  426. MODULE_DEVICE_TABLE(of, omap_dmic_of_match);
  427. static struct platform_driver asoc_dmic_driver = {
  428. .driver = {
  429. .name = "omap-dmic",
  430. .of_match_table = omap_dmic_of_match,
  431. },
  432. .probe = asoc_dmic_probe,
  433. };
  434. module_platform_driver(asoc_dmic_driver);
  435. MODULE_ALIAS("platform:omap-dmic");
  436. MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
  437. MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
  438. MODULE_LICENSE("GPL");