tegra20_das.h 4.5 KB

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  1. /*
  2. * tegra20_das.h - Definitions for Tegra20 DAS driver
  3. *
  4. * Author: Stephen Warren <swarren@nvidia.com>
  5. * Copyright (C) 2010,2012 - NVIDIA, Inc.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * version 2 as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  19. * 02110-1301 USA
  20. *
  21. */
  22. #ifndef __TEGRA20_DAS_H__
  23. #define __TEGRA20_DAS_H__
  24. /* Register TEGRA20_DAS_DAP_CTRL_SEL */
  25. #define TEGRA20_DAS_DAP_CTRL_SEL 0x00
  26. #define TEGRA20_DAS_DAP_CTRL_SEL_COUNT 5
  27. #define TEGRA20_DAS_DAP_CTRL_SEL_STRIDE 4
  28. #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P 31
  29. #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S 1
  30. #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P 30
  31. #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S 1
  32. #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P 29
  33. #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S 1
  34. #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P 0
  35. #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S 5
  36. /* Values for field TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */
  37. #define TEGRA20_DAS_DAP_SEL_DAC1 0
  38. #define TEGRA20_DAS_DAP_SEL_DAC2 1
  39. #define TEGRA20_DAS_DAP_SEL_DAC3 2
  40. #define TEGRA20_DAS_DAP_SEL_DAP1 16
  41. #define TEGRA20_DAS_DAP_SEL_DAP2 17
  42. #define TEGRA20_DAS_DAP_SEL_DAP3 18
  43. #define TEGRA20_DAS_DAP_SEL_DAP4 19
  44. #define TEGRA20_DAS_DAP_SEL_DAP5 20
  45. /* Register TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL */
  46. #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL 0x40
  47. #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT 3
  48. #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE 4
  49. #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P 28
  50. #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S 4
  51. #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P 24
  52. #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S 4
  53. #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P 0
  54. #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S 4
  55. /*
  56. * Values for:
  57. * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL
  58. * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL
  59. * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL
  60. */
  61. #define TEGRA20_DAS_DAC_SEL_DAP1 0
  62. #define TEGRA20_DAS_DAC_SEL_DAP2 1
  63. #define TEGRA20_DAS_DAC_SEL_DAP3 2
  64. #define TEGRA20_DAS_DAC_SEL_DAP4 3
  65. #define TEGRA20_DAS_DAC_SEL_DAP5 4
  66. /*
  67. * Names/IDs of the DACs/DAPs.
  68. */
  69. #define TEGRA20_DAS_DAP_ID_1 0
  70. #define TEGRA20_DAS_DAP_ID_2 1
  71. #define TEGRA20_DAS_DAP_ID_3 2
  72. #define TEGRA20_DAS_DAP_ID_4 3
  73. #define TEGRA20_DAS_DAP_ID_5 4
  74. #define TEGRA20_DAS_DAC_ID_1 0
  75. #define TEGRA20_DAS_DAC_ID_2 1
  76. #define TEGRA20_DAS_DAC_ID_3 2
  77. struct tegra20_das {
  78. struct device *dev;
  79. struct regmap *regmap;
  80. };
  81. /*
  82. * Terminology:
  83. * DAS: Digital audio switch (HW module controlled by this driver)
  84. * DAP: Digital audio port (port/pins on Tegra device)
  85. * DAC: Digital audio controller (e.g. I2S or AC97 controller elsewhere)
  86. *
  87. * The Tegra DAS is a mux/cross-bar which can connect each DAP to a specific
  88. * DAC, or another DAP. When DAPs are connected, one must be the master and
  89. * one the slave. Each DAC allows selection of a specific DAP for input, to
  90. * cater for the case where N DAPs are connected to 1 DAC for broadcast
  91. * output.
  92. *
  93. * This driver is dumb; no attempt is made to ensure that a valid routing
  94. * configuration is programmed.
  95. */
  96. /*
  97. * Connect a DAP to to a DAC
  98. * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
  99. * dac_sel: DAC to connect to: TEGRA20_DAS_DAP_SEL_DAC*
  100. */
  101. extern int tegra20_das_connect_dap_to_dac(int dap_id, int dac_sel);
  102. /*
  103. * Connect a DAP to to another DAP
  104. * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
  105. * other_dap_sel: DAP to connect to: TEGRA20_DAS_DAP_SEL_DAP*
  106. * master: Is this DAP the master (1) or slave (0)
  107. * sdata1rx: Is this DAP's SDATA1 pin RX (1) or TX (0)
  108. * sdata2rx: Is this DAP's SDATA2 pin RX (1) or TX (0)
  109. */
  110. extern int tegra20_das_connect_dap_to_dap(int dap_id, int other_dap_sel,
  111. int master, int sdata1rx,
  112. int sdata2rx);
  113. /*
  114. * Connect a DAC's input to a DAP
  115. * (DAC outputs are selected by the DAP)
  116. * dac_id: DAC ID to connect: TEGRA20_DAS_DAC_ID_*
  117. * dap_sel: DAP to receive input from: TEGRA20_DAS_DAC_SEL_DAP*
  118. */
  119. extern int tegra20_das_connect_dac_to_dap(int dac_id, int dap_sel);
  120. #endif