amd7930.c 30 KB

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  1. /*
  2. * Driver for AMD7930 sound chips found on Sparcs.
  3. * Copyright (C) 2002, 2008 David S. Miller <davem@davemloft.net>
  4. *
  5. * Based entirely upon drivers/sbus/audio/amd7930.c which is:
  6. * Copyright (C) 1996,1997 Thomas K. Dyas (tdyas@eden.rutgers.edu)
  7. *
  8. * --- Notes from Thomas's original driver ---
  9. * This is the lowlevel driver for the AMD7930 audio chip found on all
  10. * sun4c machines and some sun4m machines.
  11. *
  12. * The amd7930 is actually an ISDN chip which has a very simple
  13. * integrated audio encoder/decoder. When Sun decided on what chip to
  14. * use for audio, they had the brilliant idea of using the amd7930 and
  15. * only connecting the audio encoder/decoder pins.
  16. *
  17. * Thanks to the AMD engineer who was able to get us the AMD79C30
  18. * databook which has all the programming information and gain tables.
  19. *
  20. * Advanced Micro Devices' Am79C30A is an ISDN/audio chip used in the
  21. * SparcStation 1+. The chip provides microphone and speaker interfaces
  22. * which provide mono-channel audio at 8K samples per second via either
  23. * 8-bit A-law or 8-bit mu-law encoding. Also, the chip features an
  24. * ISDN BRI Line Interface Unit (LIU), I.430 S/T physical interface,
  25. * which performs basic D channel LAPD processing and provides raw
  26. * B channel data. The digital audio channel, the two ISDN B channels,
  27. * and two 64 Kbps channels to the microprocessor are all interconnected
  28. * via a multiplexer.
  29. * --- End of notes from Thoamas's original driver ---
  30. */
  31. #include <linux/module.h>
  32. #include <linux/kernel.h>
  33. #include <linux/slab.h>
  34. #include <linux/init.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/moduleparam.h>
  37. #include <linux/of.h>
  38. #include <linux/of_device.h>
  39. #include <linux/io.h>
  40. #include <sound/core.h>
  41. #include <sound/pcm.h>
  42. #include <sound/info.h>
  43. #include <sound/control.h>
  44. #include <sound/initval.h>
  45. #include <asm/irq.h>
  46. #include <asm/prom.h>
  47. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  48. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  49. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  50. module_param_array(index, int, NULL, 0444);
  51. MODULE_PARM_DESC(index, "Index value for Sun AMD7930 soundcard.");
  52. module_param_array(id, charp, NULL, 0444);
  53. MODULE_PARM_DESC(id, "ID string for Sun AMD7930 soundcard.");
  54. module_param_array(enable, bool, NULL, 0444);
  55. MODULE_PARM_DESC(enable, "Enable Sun AMD7930 soundcard.");
  56. MODULE_AUTHOR("Thomas K. Dyas and David S. Miller");
  57. MODULE_DESCRIPTION("Sun AMD7930");
  58. MODULE_LICENSE("GPL");
  59. MODULE_SUPPORTED_DEVICE("{{Sun,AMD7930}}");
  60. /* Device register layout. */
  61. /* Register interface presented to the CPU by the amd7930. */
  62. #define AMD7930_CR 0x00UL /* Command Register (W) */
  63. #define AMD7930_IR AMD7930_CR /* Interrupt Register (R) */
  64. #define AMD7930_DR 0x01UL /* Data Register (R/W) */
  65. #define AMD7930_DSR1 0x02UL /* D-channel Status Register 1 (R) */
  66. #define AMD7930_DER 0x03UL /* D-channel Error Register (R) */
  67. #define AMD7930_DCTB 0x04UL /* D-channel Transmit Buffer (W) */
  68. #define AMD7930_DCRB AMD7930_DCTB /* D-channel Receive Buffer (R) */
  69. #define AMD7930_BBTB 0x05UL /* Bb-channel Transmit Buffer (W) */
  70. #define AMD7930_BBRB AMD7930_BBTB /* Bb-channel Receive Buffer (R) */
  71. #define AMD7930_BCTB 0x06UL /* Bc-channel Transmit Buffer (W) */
  72. #define AMD7930_BCRB AMD7930_BCTB /* Bc-channel Receive Buffer (R) */
  73. #define AMD7930_DSR2 0x07UL /* D-channel Status Register 2 (R) */
  74. /* Indirect registers in the Main Audio Processor. */
  75. struct amd7930_map {
  76. __u16 x[8];
  77. __u16 r[8];
  78. __u16 gx;
  79. __u16 gr;
  80. __u16 ger;
  81. __u16 stgr;
  82. __u16 ftgr;
  83. __u16 atgr;
  84. __u8 mmr1;
  85. __u8 mmr2;
  86. };
  87. /* After an amd7930 interrupt, reading the Interrupt Register (ir)
  88. * clears the interrupt and returns a bitmask indicating which
  89. * interrupt source(s) require service.
  90. */
  91. #define AMR_IR_DTTHRSH 0x01 /* D-channel xmit threshold */
  92. #define AMR_IR_DRTHRSH 0x02 /* D-channel recv threshold */
  93. #define AMR_IR_DSRI 0x04 /* D-channel packet status */
  94. #define AMR_IR_DERI 0x08 /* D-channel error */
  95. #define AMR_IR_BBUF 0x10 /* B-channel data xfer */
  96. #define AMR_IR_LSRI 0x20 /* LIU status */
  97. #define AMR_IR_DSR2I 0x40 /* D-channel buffer status */
  98. #define AMR_IR_MLTFRMI 0x80 /* multiframe or PP */
  99. /* The amd7930 has "indirect registers" which are accessed by writing
  100. * the register number into the Command Register and then reading or
  101. * writing values from the Data Register as appropriate. We define the
  102. * AMR_* macros to be the indirect register numbers and AM_* macros to
  103. * be bits in whatever register is referred to.
  104. */
  105. /* Initialization */
  106. #define AMR_INIT 0x21
  107. #define AM_INIT_ACTIVE 0x01
  108. #define AM_INIT_DATAONLY 0x02
  109. #define AM_INIT_POWERDOWN 0x03
  110. #define AM_INIT_DISABLE_INTS 0x04
  111. #define AMR_INIT2 0x20
  112. #define AM_INIT2_ENABLE_POWERDOWN 0x20
  113. #define AM_INIT2_ENABLE_MULTIFRAME 0x10
  114. /* Line Interface Unit */
  115. #define AMR_LIU_LSR 0xA1
  116. #define AM_LIU_LSR_STATE 0x07
  117. #define AM_LIU_LSR_F3 0x08
  118. #define AM_LIU_LSR_F7 0x10
  119. #define AM_LIU_LSR_F8 0x20
  120. #define AM_LIU_LSR_HSW 0x40
  121. #define AM_LIU_LSR_HSW_CHG 0x80
  122. #define AMR_LIU_LPR 0xA2
  123. #define AMR_LIU_LMR1 0xA3
  124. #define AM_LIU_LMR1_B1_ENABL 0x01
  125. #define AM_LIU_LMR1_B2_ENABL 0x02
  126. #define AM_LIU_LMR1_F_DISABL 0x04
  127. #define AM_LIU_LMR1_FA_DISABL 0x08
  128. #define AM_LIU_LMR1_REQ_ACTIV 0x10
  129. #define AM_LIU_LMR1_F8_F3 0x20
  130. #define AM_LIU_LMR1_LIU_ENABL 0x40
  131. #define AMR_LIU_LMR2 0xA4
  132. #define AM_LIU_LMR2_DECHO 0x01
  133. #define AM_LIU_LMR2_DLOOP 0x02
  134. #define AM_LIU_LMR2_DBACKOFF 0x04
  135. #define AM_LIU_LMR2_EN_F3_INT 0x08
  136. #define AM_LIU_LMR2_EN_F8_INT 0x10
  137. #define AM_LIU_LMR2_EN_HSW_INT 0x20
  138. #define AM_LIU_LMR2_EN_F7_INT 0x40
  139. #define AMR_LIU_2_4 0xA5
  140. #define AMR_LIU_MF 0xA6
  141. #define AMR_LIU_MFSB 0xA7
  142. #define AMR_LIU_MFQB 0xA8
  143. /* Multiplexor */
  144. #define AMR_MUX_MCR1 0x41
  145. #define AMR_MUX_MCR2 0x42
  146. #define AMR_MUX_MCR3 0x43
  147. #define AM_MUX_CHANNEL_B1 0x01
  148. #define AM_MUX_CHANNEL_B2 0x02
  149. #define AM_MUX_CHANNEL_Ba 0x03
  150. #define AM_MUX_CHANNEL_Bb 0x04
  151. #define AM_MUX_CHANNEL_Bc 0x05
  152. #define AM_MUX_CHANNEL_Bd 0x06
  153. #define AM_MUX_CHANNEL_Be 0x07
  154. #define AM_MUX_CHANNEL_Bf 0x08
  155. #define AMR_MUX_MCR4 0x44
  156. #define AM_MUX_MCR4_ENABLE_INTS 0x08
  157. #define AM_MUX_MCR4_REVERSE_Bb 0x10
  158. #define AM_MUX_MCR4_REVERSE_Bc 0x20
  159. #define AMR_MUX_1_4 0x45
  160. /* Main Audio Processor */
  161. #define AMR_MAP_X 0x61
  162. #define AMR_MAP_R 0x62
  163. #define AMR_MAP_GX 0x63
  164. #define AMR_MAP_GR 0x64
  165. #define AMR_MAP_GER 0x65
  166. #define AMR_MAP_STGR 0x66
  167. #define AMR_MAP_FTGR_1_2 0x67
  168. #define AMR_MAP_ATGR_1_2 0x68
  169. #define AMR_MAP_MMR1 0x69
  170. #define AM_MAP_MMR1_ALAW 0x01
  171. #define AM_MAP_MMR1_GX 0x02
  172. #define AM_MAP_MMR1_GR 0x04
  173. #define AM_MAP_MMR1_GER 0x08
  174. #define AM_MAP_MMR1_X 0x10
  175. #define AM_MAP_MMR1_R 0x20
  176. #define AM_MAP_MMR1_STG 0x40
  177. #define AM_MAP_MMR1_LOOPBACK 0x80
  178. #define AMR_MAP_MMR2 0x6A
  179. #define AM_MAP_MMR2_AINB 0x01
  180. #define AM_MAP_MMR2_LS 0x02
  181. #define AM_MAP_MMR2_ENABLE_DTMF 0x04
  182. #define AM_MAP_MMR2_ENABLE_TONEGEN 0x08
  183. #define AM_MAP_MMR2_ENABLE_TONERING 0x10
  184. #define AM_MAP_MMR2_DISABLE_HIGHPASS 0x20
  185. #define AM_MAP_MMR2_DISABLE_AUTOZERO 0x40
  186. #define AMR_MAP_1_10 0x6B
  187. #define AMR_MAP_MMR3 0x6C
  188. #define AMR_MAP_STRA 0x6D
  189. #define AMR_MAP_STRF 0x6E
  190. #define AMR_MAP_PEAKX 0x70
  191. #define AMR_MAP_PEAKR 0x71
  192. #define AMR_MAP_15_16 0x72
  193. /* Data Link Controller */
  194. #define AMR_DLC_FRAR_1_2_3 0x81
  195. #define AMR_DLC_SRAR_1_2_3 0x82
  196. #define AMR_DLC_TAR 0x83
  197. #define AMR_DLC_DRLR 0x84
  198. #define AMR_DLC_DTCR 0x85
  199. #define AMR_DLC_DMR1 0x86
  200. #define AMR_DLC_DMR1_DTTHRSH_INT 0x01
  201. #define AMR_DLC_DMR1_DRTHRSH_INT 0x02
  202. #define AMR_DLC_DMR1_TAR_ENABL 0x04
  203. #define AMR_DLC_DMR1_EORP_INT 0x08
  204. #define AMR_DLC_DMR1_EN_ADDR1 0x10
  205. #define AMR_DLC_DMR1_EN_ADDR2 0x20
  206. #define AMR_DLC_DMR1_EN_ADDR3 0x40
  207. #define AMR_DLC_DMR1_EN_ADDR4 0x80
  208. #define AMR_DLC_DMR1_EN_ADDRS 0xf0
  209. #define AMR_DLC_DMR2 0x87
  210. #define AMR_DLC_DMR2_RABRT_INT 0x01
  211. #define AMR_DLC_DMR2_RESID_INT 0x02
  212. #define AMR_DLC_DMR2_COLL_INT 0x04
  213. #define AMR_DLC_DMR2_FCS_INT 0x08
  214. #define AMR_DLC_DMR2_OVFL_INT 0x10
  215. #define AMR_DLC_DMR2_UNFL_INT 0x20
  216. #define AMR_DLC_DMR2_OVRN_INT 0x40
  217. #define AMR_DLC_DMR2_UNRN_INT 0x80
  218. #define AMR_DLC_1_7 0x88
  219. #define AMR_DLC_DRCR 0x89
  220. #define AMR_DLC_RNGR1 0x8A
  221. #define AMR_DLC_RNGR2 0x8B
  222. #define AMR_DLC_FRAR4 0x8C
  223. #define AMR_DLC_SRAR4 0x8D
  224. #define AMR_DLC_DMR3 0x8E
  225. #define AMR_DLC_DMR3_VA_INT 0x01
  226. #define AMR_DLC_DMR3_EOTP_INT 0x02
  227. #define AMR_DLC_DMR3_LBRP_INT 0x04
  228. #define AMR_DLC_DMR3_RBA_INT 0x08
  229. #define AMR_DLC_DMR3_LBT_INT 0x10
  230. #define AMR_DLC_DMR3_TBE_INT 0x20
  231. #define AMR_DLC_DMR3_RPLOST_INT 0x40
  232. #define AMR_DLC_DMR3_KEEP_FCS 0x80
  233. #define AMR_DLC_DMR4 0x8F
  234. #define AMR_DLC_DMR4_RCV_1 0x00
  235. #define AMR_DLC_DMR4_RCV_2 0x01
  236. #define AMR_DLC_DMR4_RCV_4 0x02
  237. #define AMR_DLC_DMR4_RCV_8 0x03
  238. #define AMR_DLC_DMR4_RCV_16 0x01
  239. #define AMR_DLC_DMR4_RCV_24 0x02
  240. #define AMR_DLC_DMR4_RCV_30 0x03
  241. #define AMR_DLC_DMR4_XMT_1 0x00
  242. #define AMR_DLC_DMR4_XMT_2 0x04
  243. #define AMR_DLC_DMR4_XMT_4 0x08
  244. #define AMR_DLC_DMR4_XMT_8 0x0c
  245. #define AMR_DLC_DMR4_XMT_10 0x08
  246. #define AMR_DLC_DMR4_XMT_14 0x0c
  247. #define AMR_DLC_DMR4_IDLE_MARK 0x00
  248. #define AMR_DLC_DMR4_IDLE_FLAG 0x10
  249. #define AMR_DLC_DMR4_ADDR_BOTH 0x00
  250. #define AMR_DLC_DMR4_ADDR_1ST 0x20
  251. #define AMR_DLC_DMR4_ADDR_2ND 0xa0
  252. #define AMR_DLC_DMR4_CR_ENABLE 0x40
  253. #define AMR_DLC_12_15 0x90
  254. #define AMR_DLC_ASR 0x91
  255. #define AMR_DLC_EFCR 0x92
  256. #define AMR_DLC_EFCR_EXTEND_FIFO 0x01
  257. #define AMR_DLC_EFCR_SEC_PKT_INT 0x02
  258. #define AMR_DSR1_VADDR 0x01
  259. #define AMR_DSR1_EORP 0x02
  260. #define AMR_DSR1_PKT_IP 0x04
  261. #define AMR_DSR1_DECHO_ON 0x08
  262. #define AMR_DSR1_DLOOP_ON 0x10
  263. #define AMR_DSR1_DBACK_OFF 0x20
  264. #define AMR_DSR1_EOTP 0x40
  265. #define AMR_DSR1_CXMT_ABRT 0x80
  266. #define AMR_DSR2_LBRP 0x01
  267. #define AMR_DSR2_RBA 0x02
  268. #define AMR_DSR2_RPLOST 0x04
  269. #define AMR_DSR2_LAST_BYTE 0x08
  270. #define AMR_DSR2_TBE 0x10
  271. #define AMR_DSR2_MARK_IDLE 0x20
  272. #define AMR_DSR2_FLAG_IDLE 0x40
  273. #define AMR_DSR2_SECOND_PKT 0x80
  274. #define AMR_DER_RABRT 0x01
  275. #define AMR_DER_RFRAME 0x02
  276. #define AMR_DER_COLLISION 0x04
  277. #define AMR_DER_FCS 0x08
  278. #define AMR_DER_OVFL 0x10
  279. #define AMR_DER_UNFL 0x20
  280. #define AMR_DER_OVRN 0x40
  281. #define AMR_DER_UNRN 0x80
  282. /* Peripheral Port */
  283. #define AMR_PP_PPCR1 0xC0
  284. #define AMR_PP_PPSR 0xC1
  285. #define AMR_PP_PPIER 0xC2
  286. #define AMR_PP_MTDR 0xC3
  287. #define AMR_PP_MRDR 0xC3
  288. #define AMR_PP_CITDR0 0xC4
  289. #define AMR_PP_CIRDR0 0xC4
  290. #define AMR_PP_CITDR1 0xC5
  291. #define AMR_PP_CIRDR1 0xC5
  292. #define AMR_PP_PPCR2 0xC8
  293. #define AMR_PP_PPCR3 0xC9
  294. struct snd_amd7930 {
  295. spinlock_t lock;
  296. void __iomem *regs;
  297. u32 flags;
  298. #define AMD7930_FLAG_PLAYBACK 0x00000001
  299. #define AMD7930_FLAG_CAPTURE 0x00000002
  300. struct amd7930_map map;
  301. struct snd_card *card;
  302. struct snd_pcm *pcm;
  303. struct snd_pcm_substream *playback_substream;
  304. struct snd_pcm_substream *capture_substream;
  305. /* Playback/Capture buffer state. */
  306. unsigned char *p_orig, *p_cur;
  307. int p_left;
  308. unsigned char *c_orig, *c_cur;
  309. int c_left;
  310. int rgain;
  311. int pgain;
  312. int mgain;
  313. struct platform_device *op;
  314. unsigned int irq;
  315. struct snd_amd7930 *next;
  316. };
  317. static struct snd_amd7930 *amd7930_list;
  318. /* Idle the AMD7930 chip. The amd->lock is not held. */
  319. static __inline__ void amd7930_idle(struct snd_amd7930 *amd)
  320. {
  321. unsigned long flags;
  322. spin_lock_irqsave(&amd->lock, flags);
  323. sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
  324. sbus_writeb(0, amd->regs + AMD7930_DR);
  325. spin_unlock_irqrestore(&amd->lock, flags);
  326. }
  327. /* Enable chip interrupts. The amd->lock is not held. */
  328. static __inline__ void amd7930_enable_ints(struct snd_amd7930 *amd)
  329. {
  330. unsigned long flags;
  331. spin_lock_irqsave(&amd->lock, flags);
  332. sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
  333. sbus_writeb(AM_INIT_ACTIVE, amd->regs + AMD7930_DR);
  334. spin_unlock_irqrestore(&amd->lock, flags);
  335. }
  336. /* Disable chip interrupts. The amd->lock is not held. */
  337. static __inline__ void amd7930_disable_ints(struct snd_amd7930 *amd)
  338. {
  339. unsigned long flags;
  340. spin_lock_irqsave(&amd->lock, flags);
  341. sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
  342. sbus_writeb(AM_INIT_ACTIVE | AM_INIT_DISABLE_INTS, amd->regs + AMD7930_DR);
  343. spin_unlock_irqrestore(&amd->lock, flags);
  344. }
  345. /* Commit amd7930_map settings to the hardware.
  346. * The amd->lock is held and local interrupts are disabled.
  347. */
  348. static void __amd7930_write_map(struct snd_amd7930 *amd)
  349. {
  350. struct amd7930_map *map = &amd->map;
  351. sbus_writeb(AMR_MAP_GX, amd->regs + AMD7930_CR);
  352. sbus_writeb(((map->gx >> 0) & 0xff), amd->regs + AMD7930_DR);
  353. sbus_writeb(((map->gx >> 8) & 0xff), amd->regs + AMD7930_DR);
  354. sbus_writeb(AMR_MAP_GR, amd->regs + AMD7930_CR);
  355. sbus_writeb(((map->gr >> 0) & 0xff), amd->regs + AMD7930_DR);
  356. sbus_writeb(((map->gr >> 8) & 0xff), amd->regs + AMD7930_DR);
  357. sbus_writeb(AMR_MAP_STGR, amd->regs + AMD7930_CR);
  358. sbus_writeb(((map->stgr >> 0) & 0xff), amd->regs + AMD7930_DR);
  359. sbus_writeb(((map->stgr >> 8) & 0xff), amd->regs + AMD7930_DR);
  360. sbus_writeb(AMR_MAP_GER, amd->regs + AMD7930_CR);
  361. sbus_writeb(((map->ger >> 0) & 0xff), amd->regs + AMD7930_DR);
  362. sbus_writeb(((map->ger >> 8) & 0xff), amd->regs + AMD7930_DR);
  363. sbus_writeb(AMR_MAP_MMR1, amd->regs + AMD7930_CR);
  364. sbus_writeb(map->mmr1, amd->regs + AMD7930_DR);
  365. sbus_writeb(AMR_MAP_MMR2, amd->regs + AMD7930_CR);
  366. sbus_writeb(map->mmr2, amd->regs + AMD7930_DR);
  367. }
  368. /* gx, gr & stg gains. this table must contain 256 elements with
  369. * the 0th being "infinity" (the magic value 9008). The remaining
  370. * elements match sun's gain curve (but with higher resolution):
  371. * -18 to 0dB in .16dB steps then 0 to 12dB in .08dB steps.
  372. */
  373. static __const__ __u16 gx_coeff[256] = {
  374. 0x9008, 0x8b7c, 0x8b51, 0x8b45, 0x8b42, 0x8b3b, 0x8b36, 0x8b33,
  375. 0x8b32, 0x8b2a, 0x8b2b, 0x8b2c, 0x8b25, 0x8b23, 0x8b22, 0x8b22,
  376. 0x9122, 0x8b1a, 0x8aa3, 0x8aa3, 0x8b1c, 0x8aa6, 0x912d, 0x912b,
  377. 0x8aab, 0x8b12, 0x8aaa, 0x8ab2, 0x9132, 0x8ab4, 0x913c, 0x8abb,
  378. 0x9142, 0x9144, 0x9151, 0x8ad5, 0x8aeb, 0x8a79, 0x8a5a, 0x8a4a,
  379. 0x8b03, 0x91c2, 0x91bb, 0x8a3f, 0x8a33, 0x91b2, 0x9212, 0x9213,
  380. 0x8a2c, 0x921d, 0x8a23, 0x921a, 0x9222, 0x9223, 0x922d, 0x9231,
  381. 0x9234, 0x9242, 0x925b, 0x92dd, 0x92c1, 0x92b3, 0x92ab, 0x92a4,
  382. 0x92a2, 0x932b, 0x9341, 0x93d3, 0x93b2, 0x93a2, 0x943c, 0x94b2,
  383. 0x953a, 0x9653, 0x9782, 0x9e21, 0x9d23, 0x9cd2, 0x9c23, 0x9baa,
  384. 0x9bde, 0x9b33, 0x9b22, 0x9b1d, 0x9ab2, 0xa142, 0xa1e5, 0x9a3b,
  385. 0xa213, 0xa1a2, 0xa231, 0xa2eb, 0xa313, 0xa334, 0xa421, 0xa54b,
  386. 0xada4, 0xac23, 0xab3b, 0xaaab, 0xaa5c, 0xb1a3, 0xb2ca, 0xb3bd,
  387. 0xbe24, 0xbb2b, 0xba33, 0xc32b, 0xcb5a, 0xd2a2, 0xe31d, 0x0808,
  388. 0x72ba, 0x62c2, 0x5c32, 0x52db, 0x513e, 0x4cce, 0x43b2, 0x4243,
  389. 0x41b4, 0x3b12, 0x3bc3, 0x3df2, 0x34bd, 0x3334, 0x32c2, 0x3224,
  390. 0x31aa, 0x2a7b, 0x2aaa, 0x2b23, 0x2bba, 0x2c42, 0x2e23, 0x25bb,
  391. 0x242b, 0x240f, 0x231a, 0x22bb, 0x2241, 0x2223, 0x221f, 0x1a33,
  392. 0x1a4a, 0x1acd, 0x2132, 0x1b1b, 0x1b2c, 0x1b62, 0x1c12, 0x1c32,
  393. 0x1d1b, 0x1e71, 0x16b1, 0x1522, 0x1434, 0x1412, 0x1352, 0x1323,
  394. 0x1315, 0x12bc, 0x127a, 0x1235, 0x1226, 0x11a2, 0x1216, 0x0a2a,
  395. 0x11bc, 0x11d1, 0x1163, 0x0ac2, 0x0ab2, 0x0aab, 0x0b1b, 0x0b23,
  396. 0x0b33, 0x0c0f, 0x0bb3, 0x0c1b, 0x0c3e, 0x0cb1, 0x0d4c, 0x0ec1,
  397. 0x079a, 0x0614, 0x0521, 0x047c, 0x0422, 0x03b1, 0x03e3, 0x0333,
  398. 0x0322, 0x031c, 0x02aa, 0x02ba, 0x02f2, 0x0242, 0x0232, 0x0227,
  399. 0x0222, 0x021b, 0x01ad, 0x0212, 0x01b2, 0x01bb, 0x01cb, 0x01f6,
  400. 0x0152, 0x013a, 0x0133, 0x0131, 0x012c, 0x0123, 0x0122, 0x00a2,
  401. 0x011b, 0x011e, 0x0114, 0x00b1, 0x00aa, 0x00b3, 0x00bd, 0x00ba,
  402. 0x00c5, 0x00d3, 0x00f3, 0x0062, 0x0051, 0x0042, 0x003b, 0x0033,
  403. 0x0032, 0x002a, 0x002c, 0x0025, 0x0023, 0x0022, 0x001a, 0x0021,
  404. 0x001b, 0x001b, 0x001d, 0x0015, 0x0013, 0x0013, 0x0012, 0x0012,
  405. 0x000a, 0x000a, 0x0011, 0x0011, 0x000b, 0x000b, 0x000c, 0x000e,
  406. };
  407. static __const__ __u16 ger_coeff[] = {
  408. 0x431f, /* 5. dB */
  409. 0x331f, /* 5.5 dB */
  410. 0x40dd, /* 6. dB */
  411. 0x11dd, /* 6.5 dB */
  412. 0x440f, /* 7. dB */
  413. 0x411f, /* 7.5 dB */
  414. 0x311f, /* 8. dB */
  415. 0x5520, /* 8.5 dB */
  416. 0x10dd, /* 9. dB */
  417. 0x4211, /* 9.5 dB */
  418. 0x410f, /* 10. dB */
  419. 0x111f, /* 10.5 dB */
  420. 0x600b, /* 11. dB */
  421. 0x00dd, /* 11.5 dB */
  422. 0x4210, /* 12. dB */
  423. 0x110f, /* 13. dB */
  424. 0x7200, /* 14. dB */
  425. 0x2110, /* 15. dB */
  426. 0x2200, /* 15.9 dB */
  427. 0x000b, /* 16.9 dB */
  428. 0x000f /* 18. dB */
  429. };
  430. /* Update amd7930_map settings and program them into the hardware.
  431. * The amd->lock is held and local interrupts are disabled.
  432. */
  433. static void __amd7930_update_map(struct snd_amd7930 *amd)
  434. {
  435. struct amd7930_map *map = &amd->map;
  436. int level;
  437. map->gx = gx_coeff[amd->rgain];
  438. map->stgr = gx_coeff[amd->mgain];
  439. level = (amd->pgain * (256 + ARRAY_SIZE(ger_coeff))) >> 8;
  440. if (level >= 256) {
  441. map->ger = ger_coeff[level - 256];
  442. map->gr = gx_coeff[255];
  443. } else {
  444. map->ger = ger_coeff[0];
  445. map->gr = gx_coeff[level];
  446. }
  447. __amd7930_write_map(amd);
  448. }
  449. static irqreturn_t snd_amd7930_interrupt(int irq, void *dev_id)
  450. {
  451. struct snd_amd7930 *amd = dev_id;
  452. unsigned int elapsed;
  453. u8 ir;
  454. spin_lock(&amd->lock);
  455. elapsed = 0;
  456. ir = sbus_readb(amd->regs + AMD7930_IR);
  457. if (ir & AMR_IR_BBUF) {
  458. u8 byte;
  459. if (amd->flags & AMD7930_FLAG_PLAYBACK) {
  460. if (amd->p_left > 0) {
  461. byte = *(amd->p_cur++);
  462. amd->p_left--;
  463. sbus_writeb(byte, amd->regs + AMD7930_BBTB);
  464. if (amd->p_left == 0)
  465. elapsed |= AMD7930_FLAG_PLAYBACK;
  466. } else
  467. sbus_writeb(0, amd->regs + AMD7930_BBTB);
  468. } else if (amd->flags & AMD7930_FLAG_CAPTURE) {
  469. byte = sbus_readb(amd->regs + AMD7930_BBRB);
  470. if (amd->c_left > 0) {
  471. *(amd->c_cur++) = byte;
  472. amd->c_left--;
  473. if (amd->c_left == 0)
  474. elapsed |= AMD7930_FLAG_CAPTURE;
  475. }
  476. }
  477. }
  478. spin_unlock(&amd->lock);
  479. if (elapsed & AMD7930_FLAG_PLAYBACK)
  480. snd_pcm_period_elapsed(amd->playback_substream);
  481. else
  482. snd_pcm_period_elapsed(amd->capture_substream);
  483. return IRQ_HANDLED;
  484. }
  485. static int snd_amd7930_trigger(struct snd_amd7930 *amd, unsigned int flag, int cmd)
  486. {
  487. unsigned long flags;
  488. int result = 0;
  489. spin_lock_irqsave(&amd->lock, flags);
  490. if (cmd == SNDRV_PCM_TRIGGER_START) {
  491. if (!(amd->flags & flag)) {
  492. amd->flags |= flag;
  493. /* Enable B channel interrupts. */
  494. sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR);
  495. sbus_writeb(AM_MUX_MCR4_ENABLE_INTS, amd->regs + AMD7930_DR);
  496. }
  497. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  498. if (amd->flags & flag) {
  499. amd->flags &= ~flag;
  500. /* Disable B channel interrupts. */
  501. sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR);
  502. sbus_writeb(0, amd->regs + AMD7930_DR);
  503. }
  504. } else {
  505. result = -EINVAL;
  506. }
  507. spin_unlock_irqrestore(&amd->lock, flags);
  508. return result;
  509. }
  510. static int snd_amd7930_playback_trigger(struct snd_pcm_substream *substream,
  511. int cmd)
  512. {
  513. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  514. return snd_amd7930_trigger(amd, AMD7930_FLAG_PLAYBACK, cmd);
  515. }
  516. static int snd_amd7930_capture_trigger(struct snd_pcm_substream *substream,
  517. int cmd)
  518. {
  519. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  520. return snd_amd7930_trigger(amd, AMD7930_FLAG_CAPTURE, cmd);
  521. }
  522. static int snd_amd7930_playback_prepare(struct snd_pcm_substream *substream)
  523. {
  524. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  525. struct snd_pcm_runtime *runtime = substream->runtime;
  526. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  527. unsigned long flags;
  528. u8 new_mmr1;
  529. spin_lock_irqsave(&amd->lock, flags);
  530. amd->flags |= AMD7930_FLAG_PLAYBACK;
  531. /* Setup the pseudo-dma transfer pointers. */
  532. amd->p_orig = amd->p_cur = runtime->dma_area;
  533. amd->p_left = size;
  534. /* Put the chip into the correct encoding format. */
  535. new_mmr1 = amd->map.mmr1;
  536. if (runtime->format == SNDRV_PCM_FORMAT_A_LAW)
  537. new_mmr1 |= AM_MAP_MMR1_ALAW;
  538. else
  539. new_mmr1 &= ~AM_MAP_MMR1_ALAW;
  540. if (new_mmr1 != amd->map.mmr1) {
  541. amd->map.mmr1 = new_mmr1;
  542. __amd7930_update_map(amd);
  543. }
  544. spin_unlock_irqrestore(&amd->lock, flags);
  545. return 0;
  546. }
  547. static int snd_amd7930_capture_prepare(struct snd_pcm_substream *substream)
  548. {
  549. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  550. struct snd_pcm_runtime *runtime = substream->runtime;
  551. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  552. unsigned long flags;
  553. u8 new_mmr1;
  554. spin_lock_irqsave(&amd->lock, flags);
  555. amd->flags |= AMD7930_FLAG_CAPTURE;
  556. /* Setup the pseudo-dma transfer pointers. */
  557. amd->c_orig = amd->c_cur = runtime->dma_area;
  558. amd->c_left = size;
  559. /* Put the chip into the correct encoding format. */
  560. new_mmr1 = amd->map.mmr1;
  561. if (runtime->format == SNDRV_PCM_FORMAT_A_LAW)
  562. new_mmr1 |= AM_MAP_MMR1_ALAW;
  563. else
  564. new_mmr1 &= ~AM_MAP_MMR1_ALAW;
  565. if (new_mmr1 != amd->map.mmr1) {
  566. amd->map.mmr1 = new_mmr1;
  567. __amd7930_update_map(amd);
  568. }
  569. spin_unlock_irqrestore(&amd->lock, flags);
  570. return 0;
  571. }
  572. static snd_pcm_uframes_t snd_amd7930_playback_pointer(struct snd_pcm_substream *substream)
  573. {
  574. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  575. size_t ptr;
  576. if (!(amd->flags & AMD7930_FLAG_PLAYBACK))
  577. return 0;
  578. ptr = amd->p_cur - amd->p_orig;
  579. return bytes_to_frames(substream->runtime, ptr);
  580. }
  581. static snd_pcm_uframes_t snd_amd7930_capture_pointer(struct snd_pcm_substream *substream)
  582. {
  583. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  584. size_t ptr;
  585. if (!(amd->flags & AMD7930_FLAG_CAPTURE))
  586. return 0;
  587. ptr = amd->c_cur - amd->c_orig;
  588. return bytes_to_frames(substream->runtime, ptr);
  589. }
  590. /* Playback and capture have identical properties. */
  591. static struct snd_pcm_hardware snd_amd7930_pcm_hw =
  592. {
  593. .info = (SNDRV_PCM_INFO_MMAP |
  594. SNDRV_PCM_INFO_MMAP_VALID |
  595. SNDRV_PCM_INFO_INTERLEAVED |
  596. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  597. SNDRV_PCM_INFO_HALF_DUPLEX),
  598. .formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW,
  599. .rates = SNDRV_PCM_RATE_8000,
  600. .rate_min = 8000,
  601. .rate_max = 8000,
  602. .channels_min = 1,
  603. .channels_max = 1,
  604. .buffer_bytes_max = (64*1024),
  605. .period_bytes_min = 1,
  606. .period_bytes_max = (64*1024),
  607. .periods_min = 1,
  608. .periods_max = 1024,
  609. };
  610. static int snd_amd7930_playback_open(struct snd_pcm_substream *substream)
  611. {
  612. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  613. struct snd_pcm_runtime *runtime = substream->runtime;
  614. amd->playback_substream = substream;
  615. runtime->hw = snd_amd7930_pcm_hw;
  616. return 0;
  617. }
  618. static int snd_amd7930_capture_open(struct snd_pcm_substream *substream)
  619. {
  620. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  621. struct snd_pcm_runtime *runtime = substream->runtime;
  622. amd->capture_substream = substream;
  623. runtime->hw = snd_amd7930_pcm_hw;
  624. return 0;
  625. }
  626. static int snd_amd7930_playback_close(struct snd_pcm_substream *substream)
  627. {
  628. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  629. amd->playback_substream = NULL;
  630. return 0;
  631. }
  632. static int snd_amd7930_capture_close(struct snd_pcm_substream *substream)
  633. {
  634. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  635. amd->capture_substream = NULL;
  636. return 0;
  637. }
  638. static int snd_amd7930_hw_params(struct snd_pcm_substream *substream,
  639. struct snd_pcm_hw_params *hw_params)
  640. {
  641. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  642. }
  643. static int snd_amd7930_hw_free(struct snd_pcm_substream *substream)
  644. {
  645. return snd_pcm_lib_free_pages(substream);
  646. }
  647. static struct snd_pcm_ops snd_amd7930_playback_ops = {
  648. .open = snd_amd7930_playback_open,
  649. .close = snd_amd7930_playback_close,
  650. .ioctl = snd_pcm_lib_ioctl,
  651. .hw_params = snd_amd7930_hw_params,
  652. .hw_free = snd_amd7930_hw_free,
  653. .prepare = snd_amd7930_playback_prepare,
  654. .trigger = snd_amd7930_playback_trigger,
  655. .pointer = snd_amd7930_playback_pointer,
  656. };
  657. static struct snd_pcm_ops snd_amd7930_capture_ops = {
  658. .open = snd_amd7930_capture_open,
  659. .close = snd_amd7930_capture_close,
  660. .ioctl = snd_pcm_lib_ioctl,
  661. .hw_params = snd_amd7930_hw_params,
  662. .hw_free = snd_amd7930_hw_free,
  663. .prepare = snd_amd7930_capture_prepare,
  664. .trigger = snd_amd7930_capture_trigger,
  665. .pointer = snd_amd7930_capture_pointer,
  666. };
  667. static int snd_amd7930_pcm(struct snd_amd7930 *amd)
  668. {
  669. struct snd_pcm *pcm;
  670. int err;
  671. if ((err = snd_pcm_new(amd->card,
  672. /* ID */ "sun_amd7930",
  673. /* device */ 0,
  674. /* playback count */ 1,
  675. /* capture count */ 1, &pcm)) < 0)
  676. return err;
  677. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_amd7930_playback_ops);
  678. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_amd7930_capture_ops);
  679. pcm->private_data = amd;
  680. pcm->info_flags = 0;
  681. strcpy(pcm->name, amd->card->shortname);
  682. amd->pcm = pcm;
  683. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
  684. snd_dma_continuous_data(GFP_KERNEL),
  685. 64*1024, 64*1024);
  686. return 0;
  687. }
  688. #define VOLUME_MONITOR 0
  689. #define VOLUME_CAPTURE 1
  690. #define VOLUME_PLAYBACK 2
  691. static int snd_amd7930_info_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_info *uinfo)
  692. {
  693. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  694. uinfo->count = 1;
  695. uinfo->value.integer.min = 0;
  696. uinfo->value.integer.max = 255;
  697. return 0;
  698. }
  699. static int snd_amd7930_get_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol)
  700. {
  701. struct snd_amd7930 *amd = snd_kcontrol_chip(kctl);
  702. int type = kctl->private_value;
  703. int *swval;
  704. switch (type) {
  705. case VOLUME_MONITOR:
  706. swval = &amd->mgain;
  707. break;
  708. case VOLUME_CAPTURE:
  709. swval = &amd->rgain;
  710. break;
  711. case VOLUME_PLAYBACK:
  712. default:
  713. swval = &amd->pgain;
  714. break;
  715. }
  716. ucontrol->value.integer.value[0] = *swval;
  717. return 0;
  718. }
  719. static int snd_amd7930_put_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol)
  720. {
  721. struct snd_amd7930 *amd = snd_kcontrol_chip(kctl);
  722. unsigned long flags;
  723. int type = kctl->private_value;
  724. int *swval, change;
  725. switch (type) {
  726. case VOLUME_MONITOR:
  727. swval = &amd->mgain;
  728. break;
  729. case VOLUME_CAPTURE:
  730. swval = &amd->rgain;
  731. break;
  732. case VOLUME_PLAYBACK:
  733. default:
  734. swval = &amd->pgain;
  735. break;
  736. }
  737. spin_lock_irqsave(&amd->lock, flags);
  738. if (*swval != ucontrol->value.integer.value[0]) {
  739. *swval = ucontrol->value.integer.value[0] & 0xff;
  740. __amd7930_update_map(amd);
  741. change = 1;
  742. } else
  743. change = 0;
  744. spin_unlock_irqrestore(&amd->lock, flags);
  745. return change;
  746. }
  747. static struct snd_kcontrol_new amd7930_controls[] = {
  748. {
  749. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  750. .name = "Monitor Volume",
  751. .index = 0,
  752. .info = snd_amd7930_info_volume,
  753. .get = snd_amd7930_get_volume,
  754. .put = snd_amd7930_put_volume,
  755. .private_value = VOLUME_MONITOR,
  756. },
  757. {
  758. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  759. .name = "Capture Volume",
  760. .index = 0,
  761. .info = snd_amd7930_info_volume,
  762. .get = snd_amd7930_get_volume,
  763. .put = snd_amd7930_put_volume,
  764. .private_value = VOLUME_CAPTURE,
  765. },
  766. {
  767. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  768. .name = "Playback Volume",
  769. .index = 0,
  770. .info = snd_amd7930_info_volume,
  771. .get = snd_amd7930_get_volume,
  772. .put = snd_amd7930_put_volume,
  773. .private_value = VOLUME_PLAYBACK,
  774. },
  775. };
  776. static int snd_amd7930_mixer(struct snd_amd7930 *amd)
  777. {
  778. struct snd_card *card;
  779. int idx, err;
  780. if (snd_BUG_ON(!amd || !amd->card))
  781. return -EINVAL;
  782. card = amd->card;
  783. strcpy(card->mixername, card->shortname);
  784. for (idx = 0; idx < ARRAY_SIZE(amd7930_controls); idx++) {
  785. if ((err = snd_ctl_add(card,
  786. snd_ctl_new1(&amd7930_controls[idx], amd))) < 0)
  787. return err;
  788. }
  789. return 0;
  790. }
  791. static int snd_amd7930_free(struct snd_amd7930 *amd)
  792. {
  793. struct platform_device *op = amd->op;
  794. amd7930_idle(amd);
  795. if (amd->irq)
  796. free_irq(amd->irq, amd);
  797. if (amd->regs)
  798. of_iounmap(&op->resource[0], amd->regs,
  799. resource_size(&op->resource[0]));
  800. kfree(amd);
  801. return 0;
  802. }
  803. static int snd_amd7930_dev_free(struct snd_device *device)
  804. {
  805. struct snd_amd7930 *amd = device->device_data;
  806. return snd_amd7930_free(amd);
  807. }
  808. static struct snd_device_ops snd_amd7930_dev_ops = {
  809. .dev_free = snd_amd7930_dev_free,
  810. };
  811. static int snd_amd7930_create(struct snd_card *card,
  812. struct platform_device *op,
  813. int irq, int dev,
  814. struct snd_amd7930 **ramd)
  815. {
  816. struct snd_amd7930 *amd;
  817. unsigned long flags;
  818. int err;
  819. *ramd = NULL;
  820. amd = kzalloc(sizeof(*amd), GFP_KERNEL);
  821. if (amd == NULL)
  822. return -ENOMEM;
  823. spin_lock_init(&amd->lock);
  824. amd->card = card;
  825. amd->op = op;
  826. amd->regs = of_ioremap(&op->resource[0], 0,
  827. resource_size(&op->resource[0]), "amd7930");
  828. if (!amd->regs) {
  829. snd_printk(KERN_ERR
  830. "amd7930-%d: Unable to map chip registers.\n", dev);
  831. kfree(amd);
  832. return -EIO;
  833. }
  834. amd7930_idle(amd);
  835. if (request_irq(irq, snd_amd7930_interrupt,
  836. IRQF_SHARED, "amd7930", amd)) {
  837. snd_printk(KERN_ERR "amd7930-%d: Unable to grab IRQ %d\n",
  838. dev, irq);
  839. snd_amd7930_free(amd);
  840. return -EBUSY;
  841. }
  842. amd->irq = irq;
  843. amd7930_enable_ints(amd);
  844. spin_lock_irqsave(&amd->lock, flags);
  845. amd->rgain = 128;
  846. amd->pgain = 200;
  847. amd->mgain = 0;
  848. memset(&amd->map, 0, sizeof(amd->map));
  849. amd->map.mmr1 = (AM_MAP_MMR1_GX | AM_MAP_MMR1_GER |
  850. AM_MAP_MMR1_GR | AM_MAP_MMR1_STG);
  851. amd->map.mmr2 = (AM_MAP_MMR2_LS | AM_MAP_MMR2_AINB);
  852. __amd7930_update_map(amd);
  853. /* Always MUX audio (Ba) to channel Bb. */
  854. sbus_writeb(AMR_MUX_MCR1, amd->regs + AMD7930_CR);
  855. sbus_writeb(AM_MUX_CHANNEL_Ba | (AM_MUX_CHANNEL_Bb << 4),
  856. amd->regs + AMD7930_DR);
  857. spin_unlock_irqrestore(&amd->lock, flags);
  858. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  859. amd, &snd_amd7930_dev_ops)) < 0) {
  860. snd_amd7930_free(amd);
  861. return err;
  862. }
  863. *ramd = amd;
  864. return 0;
  865. }
  866. static int amd7930_sbus_probe(struct platform_device *op)
  867. {
  868. struct resource *rp = &op->resource[0];
  869. static int dev_num;
  870. struct snd_card *card;
  871. struct snd_amd7930 *amd;
  872. int err, irq;
  873. irq = op->archdata.irqs[0];
  874. if (dev_num >= SNDRV_CARDS)
  875. return -ENODEV;
  876. if (!enable[dev_num]) {
  877. dev_num++;
  878. return -ENOENT;
  879. }
  880. err = snd_card_new(&op->dev, index[dev_num], id[dev_num],
  881. THIS_MODULE, 0, &card);
  882. if (err < 0)
  883. return err;
  884. strcpy(card->driver, "AMD7930");
  885. strcpy(card->shortname, "Sun AMD7930");
  886. sprintf(card->longname, "%s at 0x%02lx:0x%08Lx, irq %d",
  887. card->shortname,
  888. rp->flags & 0xffL,
  889. (unsigned long long)rp->start,
  890. irq);
  891. if ((err = snd_amd7930_create(card, op,
  892. irq, dev_num, &amd)) < 0)
  893. goto out_err;
  894. if ((err = snd_amd7930_pcm(amd)) < 0)
  895. goto out_err;
  896. if ((err = snd_amd7930_mixer(amd)) < 0)
  897. goto out_err;
  898. if ((err = snd_card_register(card)) < 0)
  899. goto out_err;
  900. amd->next = amd7930_list;
  901. amd7930_list = amd;
  902. dev_num++;
  903. return 0;
  904. out_err:
  905. snd_card_free(card);
  906. return err;
  907. }
  908. static const struct of_device_id amd7930_match[] = {
  909. {
  910. .name = "audio",
  911. },
  912. {},
  913. };
  914. MODULE_DEVICE_TABLE(of, amd7930_match);
  915. static struct platform_driver amd7930_sbus_driver = {
  916. .driver = {
  917. .name = "audio",
  918. .of_match_table = amd7930_match,
  919. },
  920. .probe = amd7930_sbus_probe,
  921. };
  922. static int __init amd7930_init(void)
  923. {
  924. return platform_driver_register(&amd7930_sbus_driver);
  925. }
  926. static void __exit amd7930_exit(void)
  927. {
  928. struct snd_amd7930 *p = amd7930_list;
  929. while (p != NULL) {
  930. struct snd_amd7930 *next = p->next;
  931. snd_card_free(p->card);
  932. p = next;
  933. }
  934. amd7930_list = NULL;
  935. platform_driver_unregister(&amd7930_sbus_driver);
  936. }
  937. module_init(amd7930_init);
  938. module_exit(amd7930_exit);