cs4231.c 56 KB

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  1. /*
  2. * Driver for CS4231 sound chips found on Sparcs.
  3. * Copyright (C) 2002, 2008 David S. Miller <davem@davemloft.net>
  4. *
  5. * Based entirely upon drivers/sbus/audio/cs4231.c which is:
  6. * Copyright (C) 1996, 1997, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
  7. * and also sound/isa/cs423x/cs4231_lib.c which is:
  8. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/delay.h>
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/moduleparam.h>
  16. #include <linux/irq.h>
  17. #include <linux/io.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/info.h>
  23. #include <sound/control.h>
  24. #include <sound/timer.h>
  25. #include <sound/initval.h>
  26. #include <sound/pcm_params.h>
  27. #ifdef CONFIG_SBUS
  28. #define SBUS_SUPPORT
  29. #endif
  30. #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
  31. #define EBUS_SUPPORT
  32. #include <linux/pci.h>
  33. #include <asm/ebus_dma.h>
  34. #endif
  35. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  36. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  37. /* Enable this card */
  38. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  39. module_param_array(index, int, NULL, 0444);
  40. MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard.");
  41. module_param_array(id, charp, NULL, 0444);
  42. MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard.");
  43. module_param_array(enable, bool, NULL, 0444);
  44. MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard.");
  45. MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
  46. MODULE_DESCRIPTION("Sun CS4231");
  47. MODULE_LICENSE("GPL");
  48. MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
  49. #ifdef SBUS_SUPPORT
  50. struct sbus_dma_info {
  51. spinlock_t lock; /* DMA access lock */
  52. int dir;
  53. void __iomem *regs;
  54. };
  55. #endif
  56. struct snd_cs4231;
  57. struct cs4231_dma_control {
  58. void (*prepare)(struct cs4231_dma_control *dma_cont,
  59. int dir);
  60. void (*enable)(struct cs4231_dma_control *dma_cont, int on);
  61. int (*request)(struct cs4231_dma_control *dma_cont,
  62. dma_addr_t bus_addr, size_t len);
  63. unsigned int (*address)(struct cs4231_dma_control *dma_cont);
  64. #ifdef EBUS_SUPPORT
  65. struct ebus_dma_info ebus_info;
  66. #endif
  67. #ifdef SBUS_SUPPORT
  68. struct sbus_dma_info sbus_info;
  69. #endif
  70. };
  71. struct snd_cs4231 {
  72. spinlock_t lock; /* registers access lock */
  73. void __iomem *port;
  74. struct cs4231_dma_control p_dma;
  75. struct cs4231_dma_control c_dma;
  76. u32 flags;
  77. #define CS4231_FLAG_EBUS 0x00000001
  78. #define CS4231_FLAG_PLAYBACK 0x00000002
  79. #define CS4231_FLAG_CAPTURE 0x00000004
  80. struct snd_card *card;
  81. struct snd_pcm *pcm;
  82. struct snd_pcm_substream *playback_substream;
  83. unsigned int p_periods_sent;
  84. struct snd_pcm_substream *capture_substream;
  85. unsigned int c_periods_sent;
  86. struct snd_timer *timer;
  87. unsigned short mode;
  88. #define CS4231_MODE_NONE 0x0000
  89. #define CS4231_MODE_PLAY 0x0001
  90. #define CS4231_MODE_RECORD 0x0002
  91. #define CS4231_MODE_TIMER 0x0004
  92. #define CS4231_MODE_OPEN (CS4231_MODE_PLAY | CS4231_MODE_RECORD | \
  93. CS4231_MODE_TIMER)
  94. unsigned char image[32]; /* registers image */
  95. int mce_bit;
  96. int calibrate_mute;
  97. struct mutex mce_mutex; /* mutex for mce register */
  98. struct mutex open_mutex; /* mutex for ALSA open/close */
  99. struct platform_device *op;
  100. unsigned int irq[2];
  101. unsigned int regs_size;
  102. struct snd_cs4231 *next;
  103. };
  104. /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
  105. * now.... -DaveM
  106. */
  107. /* IO ports */
  108. #include <sound/cs4231-regs.h>
  109. /* XXX offsets are different than PC ISA chips... */
  110. #define CS4231U(chip, x) ((chip)->port + ((c_d_c_CS4231##x) << 2))
  111. /* SBUS DMA register defines. */
  112. #define APCCSR 0x10UL /* APC DMA CSR */
  113. #define APCCVA 0x20UL /* APC Capture DMA Address */
  114. #define APCCC 0x24UL /* APC Capture Count */
  115. #define APCCNVA 0x28UL /* APC Capture DMA Next Address */
  116. #define APCCNC 0x2cUL /* APC Capture Next Count */
  117. #define APCPVA 0x30UL /* APC Play DMA Address */
  118. #define APCPC 0x34UL /* APC Play Count */
  119. #define APCPNVA 0x38UL /* APC Play DMA Next Address */
  120. #define APCPNC 0x3cUL /* APC Play Next Count */
  121. /* Defines for SBUS DMA-routines */
  122. #define APCVA 0x0UL /* APC DMA Address */
  123. #define APCC 0x4UL /* APC Count */
  124. #define APCNVA 0x8UL /* APC DMA Next Address */
  125. #define APCNC 0xcUL /* APC Next Count */
  126. #define APC_PLAY 0x30UL /* Play registers start at 0x30 */
  127. #define APC_RECORD 0x20UL /* Record registers start at 0x20 */
  128. /* APCCSR bits */
  129. #define APC_INT_PENDING 0x800000 /* Interrupt Pending */
  130. #define APC_PLAY_INT 0x400000 /* Playback interrupt */
  131. #define APC_CAPT_INT 0x200000 /* Capture interrupt */
  132. #define APC_GENL_INT 0x100000 /* General interrupt */
  133. #define APC_XINT_ENA 0x80000 /* General ext int. enable */
  134. #define APC_XINT_PLAY 0x40000 /* Playback ext intr */
  135. #define APC_XINT_CAPT 0x20000 /* Capture ext intr */
  136. #define APC_XINT_GENL 0x10000 /* Error ext intr */
  137. #define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
  138. #define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
  139. #define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
  140. #define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
  141. #define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
  142. #define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
  143. #define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
  144. #define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
  145. #define APC_PPAUSE 0x80 /* Pause the play DMA */
  146. #define APC_CPAUSE 0x40 /* Pause the capture DMA */
  147. #define APC_CDC_RESET 0x20 /* CODEC RESET */
  148. #define APC_PDMA_READY 0x08 /* Play DMA Go */
  149. #define APC_CDMA_READY 0x04 /* Capture DMA Go */
  150. #define APC_CHIP_RESET 0x01 /* Reset the chip */
  151. /* EBUS DMA register offsets */
  152. #define EBDMA_CSR 0x00UL /* Control/Status */
  153. #define EBDMA_ADDR 0x04UL /* DMA Address */
  154. #define EBDMA_COUNT 0x08UL /* DMA Count */
  155. /*
  156. * Some variables
  157. */
  158. static unsigned char freq_bits[14] = {
  159. /* 5510 */ 0x00 | CS4231_XTAL2,
  160. /* 6620 */ 0x0E | CS4231_XTAL2,
  161. /* 8000 */ 0x00 | CS4231_XTAL1,
  162. /* 9600 */ 0x0E | CS4231_XTAL1,
  163. /* 11025 */ 0x02 | CS4231_XTAL2,
  164. /* 16000 */ 0x02 | CS4231_XTAL1,
  165. /* 18900 */ 0x04 | CS4231_XTAL2,
  166. /* 22050 */ 0x06 | CS4231_XTAL2,
  167. /* 27042 */ 0x04 | CS4231_XTAL1,
  168. /* 32000 */ 0x06 | CS4231_XTAL1,
  169. /* 33075 */ 0x0C | CS4231_XTAL2,
  170. /* 37800 */ 0x08 | CS4231_XTAL2,
  171. /* 44100 */ 0x0A | CS4231_XTAL2,
  172. /* 48000 */ 0x0C | CS4231_XTAL1
  173. };
  174. static unsigned int rates[14] = {
  175. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  176. 27042, 32000, 33075, 37800, 44100, 48000
  177. };
  178. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  179. .count = ARRAY_SIZE(rates),
  180. .list = rates,
  181. };
  182. static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
  183. {
  184. return snd_pcm_hw_constraint_list(runtime, 0,
  185. SNDRV_PCM_HW_PARAM_RATE,
  186. &hw_constraints_rates);
  187. }
  188. static unsigned char snd_cs4231_original_image[32] =
  189. {
  190. 0x00, /* 00/00 - lic */
  191. 0x00, /* 01/01 - ric */
  192. 0x9f, /* 02/02 - la1ic */
  193. 0x9f, /* 03/03 - ra1ic */
  194. 0x9f, /* 04/04 - la2ic */
  195. 0x9f, /* 05/05 - ra2ic */
  196. 0xbf, /* 06/06 - loc */
  197. 0xbf, /* 07/07 - roc */
  198. 0x20, /* 08/08 - pdfr */
  199. CS4231_AUTOCALIB, /* 09/09 - ic */
  200. 0x00, /* 0a/10 - pc */
  201. 0x00, /* 0b/11 - ti */
  202. CS4231_MODE2, /* 0c/12 - mi */
  203. 0x00, /* 0d/13 - lbc */
  204. 0x00, /* 0e/14 - pbru */
  205. 0x00, /* 0f/15 - pbrl */
  206. 0x80, /* 10/16 - afei */
  207. 0x01, /* 11/17 - afeii */
  208. 0x9f, /* 12/18 - llic */
  209. 0x9f, /* 13/19 - rlic */
  210. 0x00, /* 14/20 - tlb */
  211. 0x00, /* 15/21 - thb */
  212. 0x00, /* 16/22 - la3mic/reserved */
  213. 0x00, /* 17/23 - ra3mic/reserved */
  214. 0x00, /* 18/24 - afs */
  215. 0x00, /* 19/25 - lamoc/version */
  216. 0x00, /* 1a/26 - mioc */
  217. 0x00, /* 1b/27 - ramoc/reserved */
  218. 0x20, /* 1c/28 - cdfr */
  219. 0x00, /* 1d/29 - res4 */
  220. 0x00, /* 1e/30 - cbru */
  221. 0x00, /* 1f/31 - cbrl */
  222. };
  223. static u8 __cs4231_readb(struct snd_cs4231 *cp, void __iomem *reg_addr)
  224. {
  225. if (cp->flags & CS4231_FLAG_EBUS)
  226. return readb(reg_addr);
  227. else
  228. return sbus_readb(reg_addr);
  229. }
  230. static void __cs4231_writeb(struct snd_cs4231 *cp, u8 val,
  231. void __iomem *reg_addr)
  232. {
  233. if (cp->flags & CS4231_FLAG_EBUS)
  234. return writeb(val, reg_addr);
  235. else
  236. return sbus_writeb(val, reg_addr);
  237. }
  238. /*
  239. * Basic I/O functions
  240. */
  241. static void snd_cs4231_ready(struct snd_cs4231 *chip)
  242. {
  243. int timeout;
  244. for (timeout = 250; timeout > 0; timeout--) {
  245. int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  246. if ((val & CS4231_INIT) == 0)
  247. break;
  248. udelay(100);
  249. }
  250. }
  251. static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg,
  252. unsigned char value)
  253. {
  254. snd_cs4231_ready(chip);
  255. #ifdef CONFIG_SND_DEBUG
  256. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  257. snd_printdd("out: auto calibration time out - reg = 0x%x, "
  258. "value = 0x%x\n",
  259. reg, value);
  260. #endif
  261. __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
  262. wmb();
  263. __cs4231_writeb(chip, value, CS4231U(chip, REG));
  264. mb();
  265. }
  266. static inline void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
  267. unsigned char mask, unsigned char value)
  268. {
  269. unsigned char tmp = (chip->image[reg] & mask) | value;
  270. chip->image[reg] = tmp;
  271. if (!chip->calibrate_mute)
  272. snd_cs4231_dout(chip, reg, tmp);
  273. }
  274. static void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg,
  275. unsigned char value)
  276. {
  277. snd_cs4231_dout(chip, reg, value);
  278. chip->image[reg] = value;
  279. mb();
  280. }
  281. static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
  282. {
  283. snd_cs4231_ready(chip);
  284. #ifdef CONFIG_SND_DEBUG
  285. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  286. snd_printdd("in: auto calibration time out - reg = 0x%x\n",
  287. reg);
  288. #endif
  289. __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
  290. mb();
  291. return __cs4231_readb(chip, CS4231U(chip, REG));
  292. }
  293. /*
  294. * CS4231 detection / MCE routines
  295. */
  296. static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
  297. {
  298. int timeout;
  299. /* looks like this sequence is proper for CS4231A chip (GUS MAX) */
  300. for (timeout = 5; timeout > 0; timeout--)
  301. __cs4231_readb(chip, CS4231U(chip, REGSEL));
  302. /* end of cleanup sequence */
  303. for (timeout = 500; timeout > 0; timeout--) {
  304. int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  305. if ((val & CS4231_INIT) == 0)
  306. break;
  307. msleep(1);
  308. }
  309. }
  310. static void snd_cs4231_mce_up(struct snd_cs4231 *chip)
  311. {
  312. unsigned long flags;
  313. int timeout;
  314. spin_lock_irqsave(&chip->lock, flags);
  315. snd_cs4231_ready(chip);
  316. #ifdef CONFIG_SND_DEBUG
  317. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  318. snd_printdd("mce_up - auto calibration time out (0)\n");
  319. #endif
  320. chip->mce_bit |= CS4231_MCE;
  321. timeout = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  322. if (timeout == 0x80)
  323. snd_printdd("mce_up [%p]: serious init problem - "
  324. "codec still busy\n",
  325. chip->port);
  326. if (!(timeout & CS4231_MCE))
  327. __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f),
  328. CS4231U(chip, REGSEL));
  329. spin_unlock_irqrestore(&chip->lock, flags);
  330. }
  331. static void snd_cs4231_mce_down(struct snd_cs4231 *chip)
  332. {
  333. unsigned long flags, timeout;
  334. int reg;
  335. snd_cs4231_busy_wait(chip);
  336. spin_lock_irqsave(&chip->lock, flags);
  337. #ifdef CONFIG_SND_DEBUG
  338. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  339. snd_printdd("mce_down [%p] - auto calibration time out (0)\n",
  340. CS4231U(chip, REGSEL));
  341. #endif
  342. chip->mce_bit &= ~CS4231_MCE;
  343. reg = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  344. __cs4231_writeb(chip, chip->mce_bit | (reg & 0x1f),
  345. CS4231U(chip, REGSEL));
  346. if (reg == 0x80)
  347. snd_printdd("mce_down [%p]: serious init problem "
  348. "- codec still busy\n", chip->port);
  349. if ((reg & CS4231_MCE) == 0) {
  350. spin_unlock_irqrestore(&chip->lock, flags);
  351. return;
  352. }
  353. /*
  354. * Wait for auto-calibration (AC) process to finish, i.e. ACI to go low.
  355. */
  356. timeout = jiffies + msecs_to_jiffies(250);
  357. do {
  358. spin_unlock_irqrestore(&chip->lock, flags);
  359. msleep(1);
  360. spin_lock_irqsave(&chip->lock, flags);
  361. reg = snd_cs4231_in(chip, CS4231_TEST_INIT);
  362. reg &= CS4231_CALIB_IN_PROGRESS;
  363. } while (reg && time_before(jiffies, timeout));
  364. spin_unlock_irqrestore(&chip->lock, flags);
  365. if (reg)
  366. snd_printk(KERN_ERR
  367. "mce_down - auto calibration time out (2)\n");
  368. }
  369. static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont,
  370. struct snd_pcm_substream *substream,
  371. unsigned int *periods_sent)
  372. {
  373. struct snd_pcm_runtime *runtime = substream->runtime;
  374. while (1) {
  375. unsigned int period_size = snd_pcm_lib_period_bytes(substream);
  376. unsigned int offset = period_size * (*periods_sent);
  377. if (WARN_ON(period_size >= (1 << 24)))
  378. return;
  379. if (dma_cont->request(dma_cont,
  380. runtime->dma_addr + offset, period_size))
  381. return;
  382. (*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
  383. }
  384. }
  385. static void cs4231_dma_trigger(struct snd_pcm_substream *substream,
  386. unsigned int what, int on)
  387. {
  388. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  389. struct cs4231_dma_control *dma_cont;
  390. if (what & CS4231_PLAYBACK_ENABLE) {
  391. dma_cont = &chip->p_dma;
  392. if (on) {
  393. dma_cont->prepare(dma_cont, 0);
  394. dma_cont->enable(dma_cont, 1);
  395. snd_cs4231_advance_dma(dma_cont,
  396. chip->playback_substream,
  397. &chip->p_periods_sent);
  398. } else {
  399. dma_cont->enable(dma_cont, 0);
  400. }
  401. }
  402. if (what & CS4231_RECORD_ENABLE) {
  403. dma_cont = &chip->c_dma;
  404. if (on) {
  405. dma_cont->prepare(dma_cont, 1);
  406. dma_cont->enable(dma_cont, 1);
  407. snd_cs4231_advance_dma(dma_cont,
  408. chip->capture_substream,
  409. &chip->c_periods_sent);
  410. } else {
  411. dma_cont->enable(dma_cont, 0);
  412. }
  413. }
  414. }
  415. static int snd_cs4231_trigger(struct snd_pcm_substream *substream, int cmd)
  416. {
  417. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  418. int result = 0;
  419. switch (cmd) {
  420. case SNDRV_PCM_TRIGGER_START:
  421. case SNDRV_PCM_TRIGGER_STOP:
  422. {
  423. unsigned int what = 0;
  424. struct snd_pcm_substream *s;
  425. unsigned long flags;
  426. snd_pcm_group_for_each_entry(s, substream) {
  427. if (s == chip->playback_substream) {
  428. what |= CS4231_PLAYBACK_ENABLE;
  429. snd_pcm_trigger_done(s, substream);
  430. } else if (s == chip->capture_substream) {
  431. what |= CS4231_RECORD_ENABLE;
  432. snd_pcm_trigger_done(s, substream);
  433. }
  434. }
  435. spin_lock_irqsave(&chip->lock, flags);
  436. if (cmd == SNDRV_PCM_TRIGGER_START) {
  437. cs4231_dma_trigger(substream, what, 1);
  438. chip->image[CS4231_IFACE_CTRL] |= what;
  439. } else {
  440. cs4231_dma_trigger(substream, what, 0);
  441. chip->image[CS4231_IFACE_CTRL] &= ~what;
  442. }
  443. snd_cs4231_out(chip, CS4231_IFACE_CTRL,
  444. chip->image[CS4231_IFACE_CTRL]);
  445. spin_unlock_irqrestore(&chip->lock, flags);
  446. break;
  447. }
  448. default:
  449. result = -EINVAL;
  450. break;
  451. }
  452. return result;
  453. }
  454. /*
  455. * CODEC I/O
  456. */
  457. static unsigned char snd_cs4231_get_rate(unsigned int rate)
  458. {
  459. int i;
  460. for (i = 0; i < 14; i++)
  461. if (rate == rates[i])
  462. return freq_bits[i];
  463. return freq_bits[13];
  464. }
  465. static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip, int format,
  466. int channels)
  467. {
  468. unsigned char rformat;
  469. rformat = CS4231_LINEAR_8;
  470. switch (format) {
  471. case SNDRV_PCM_FORMAT_MU_LAW:
  472. rformat = CS4231_ULAW_8;
  473. break;
  474. case SNDRV_PCM_FORMAT_A_LAW:
  475. rformat = CS4231_ALAW_8;
  476. break;
  477. case SNDRV_PCM_FORMAT_S16_LE:
  478. rformat = CS4231_LINEAR_16;
  479. break;
  480. case SNDRV_PCM_FORMAT_S16_BE:
  481. rformat = CS4231_LINEAR_16_BIG;
  482. break;
  483. case SNDRV_PCM_FORMAT_IMA_ADPCM:
  484. rformat = CS4231_ADPCM_16;
  485. break;
  486. }
  487. if (channels > 1)
  488. rformat |= CS4231_STEREO;
  489. return rformat;
  490. }
  491. static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
  492. {
  493. unsigned long flags;
  494. mute = mute ? 1 : 0;
  495. spin_lock_irqsave(&chip->lock, flags);
  496. if (chip->calibrate_mute == mute) {
  497. spin_unlock_irqrestore(&chip->lock, flags);
  498. return;
  499. }
  500. if (!mute) {
  501. snd_cs4231_dout(chip, CS4231_LEFT_INPUT,
  502. chip->image[CS4231_LEFT_INPUT]);
  503. snd_cs4231_dout(chip, CS4231_RIGHT_INPUT,
  504. chip->image[CS4231_RIGHT_INPUT]);
  505. snd_cs4231_dout(chip, CS4231_LOOPBACK,
  506. chip->image[CS4231_LOOPBACK]);
  507. }
  508. snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT,
  509. mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
  510. snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT,
  511. mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
  512. snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT,
  513. mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
  514. snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT,
  515. mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
  516. snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT,
  517. mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
  518. snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT,
  519. mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
  520. snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN,
  521. mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
  522. snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN,
  523. mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
  524. snd_cs4231_dout(chip, CS4231_MONO_CTRL,
  525. mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
  526. chip->calibrate_mute = mute;
  527. spin_unlock_irqrestore(&chip->lock, flags);
  528. }
  529. static void snd_cs4231_playback_format(struct snd_cs4231 *chip,
  530. struct snd_pcm_hw_params *params,
  531. unsigned char pdfr)
  532. {
  533. unsigned long flags;
  534. mutex_lock(&chip->mce_mutex);
  535. snd_cs4231_calibrate_mute(chip, 1);
  536. snd_cs4231_mce_up(chip);
  537. spin_lock_irqsave(&chip->lock, flags);
  538. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  539. (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
  540. (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
  541. pdfr);
  542. spin_unlock_irqrestore(&chip->lock, flags);
  543. snd_cs4231_mce_down(chip);
  544. snd_cs4231_calibrate_mute(chip, 0);
  545. mutex_unlock(&chip->mce_mutex);
  546. }
  547. static void snd_cs4231_capture_format(struct snd_cs4231 *chip,
  548. struct snd_pcm_hw_params *params,
  549. unsigned char cdfr)
  550. {
  551. unsigned long flags;
  552. mutex_lock(&chip->mce_mutex);
  553. snd_cs4231_calibrate_mute(chip, 1);
  554. snd_cs4231_mce_up(chip);
  555. spin_lock_irqsave(&chip->lock, flags);
  556. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  557. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  558. ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
  559. (cdfr & 0x0f));
  560. spin_unlock_irqrestore(&chip->lock, flags);
  561. snd_cs4231_mce_down(chip);
  562. snd_cs4231_mce_up(chip);
  563. spin_lock_irqsave(&chip->lock, flags);
  564. }
  565. snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
  566. spin_unlock_irqrestore(&chip->lock, flags);
  567. snd_cs4231_mce_down(chip);
  568. snd_cs4231_calibrate_mute(chip, 0);
  569. mutex_unlock(&chip->mce_mutex);
  570. }
  571. /*
  572. * Timer interface
  573. */
  574. static unsigned long snd_cs4231_timer_resolution(struct snd_timer *timer)
  575. {
  576. struct snd_cs4231 *chip = snd_timer_chip(timer);
  577. return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
  578. }
  579. static int snd_cs4231_timer_start(struct snd_timer *timer)
  580. {
  581. unsigned long flags;
  582. unsigned int ticks;
  583. struct snd_cs4231 *chip = snd_timer_chip(timer);
  584. spin_lock_irqsave(&chip->lock, flags);
  585. ticks = timer->sticks;
  586. if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
  587. (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
  588. (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
  589. snd_cs4231_out(chip, CS4231_TIMER_HIGH,
  590. chip->image[CS4231_TIMER_HIGH] =
  591. (unsigned char) (ticks >> 8));
  592. snd_cs4231_out(chip, CS4231_TIMER_LOW,
  593. chip->image[CS4231_TIMER_LOW] =
  594. (unsigned char) ticks);
  595. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  596. chip->image[CS4231_ALT_FEATURE_1] |
  597. CS4231_TIMER_ENABLE);
  598. }
  599. spin_unlock_irqrestore(&chip->lock, flags);
  600. return 0;
  601. }
  602. static int snd_cs4231_timer_stop(struct snd_timer *timer)
  603. {
  604. unsigned long flags;
  605. struct snd_cs4231 *chip = snd_timer_chip(timer);
  606. spin_lock_irqsave(&chip->lock, flags);
  607. chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
  608. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  609. chip->image[CS4231_ALT_FEATURE_1]);
  610. spin_unlock_irqrestore(&chip->lock, flags);
  611. return 0;
  612. }
  613. static void snd_cs4231_init(struct snd_cs4231 *chip)
  614. {
  615. unsigned long flags;
  616. snd_cs4231_mce_down(chip);
  617. #ifdef SNDRV_DEBUG_MCE
  618. snd_printdd("init: (1)\n");
  619. #endif
  620. snd_cs4231_mce_up(chip);
  621. spin_lock_irqsave(&chip->lock, flags);
  622. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
  623. CS4231_PLAYBACK_PIO |
  624. CS4231_RECORD_ENABLE |
  625. CS4231_RECORD_PIO |
  626. CS4231_CALIB_MODE);
  627. chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
  628. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  629. spin_unlock_irqrestore(&chip->lock, flags);
  630. snd_cs4231_mce_down(chip);
  631. #ifdef SNDRV_DEBUG_MCE
  632. snd_printdd("init: (2)\n");
  633. #endif
  634. snd_cs4231_mce_up(chip);
  635. spin_lock_irqsave(&chip->lock, flags);
  636. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  637. chip->image[CS4231_ALT_FEATURE_1]);
  638. spin_unlock_irqrestore(&chip->lock, flags);
  639. snd_cs4231_mce_down(chip);
  640. #ifdef SNDRV_DEBUG_MCE
  641. snd_printdd("init: (3) - afei = 0x%x\n",
  642. chip->image[CS4231_ALT_FEATURE_1]);
  643. #endif
  644. spin_lock_irqsave(&chip->lock, flags);
  645. snd_cs4231_out(chip, CS4231_ALT_FEATURE_2,
  646. chip->image[CS4231_ALT_FEATURE_2]);
  647. spin_unlock_irqrestore(&chip->lock, flags);
  648. snd_cs4231_mce_up(chip);
  649. spin_lock_irqsave(&chip->lock, flags);
  650. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  651. chip->image[CS4231_PLAYBK_FORMAT]);
  652. spin_unlock_irqrestore(&chip->lock, flags);
  653. snd_cs4231_mce_down(chip);
  654. #ifdef SNDRV_DEBUG_MCE
  655. snd_printdd("init: (4)\n");
  656. #endif
  657. snd_cs4231_mce_up(chip);
  658. spin_lock_irqsave(&chip->lock, flags);
  659. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
  660. spin_unlock_irqrestore(&chip->lock, flags);
  661. snd_cs4231_mce_down(chip);
  662. #ifdef SNDRV_DEBUG_MCE
  663. snd_printdd("init: (5)\n");
  664. #endif
  665. }
  666. static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
  667. {
  668. unsigned long flags;
  669. mutex_lock(&chip->open_mutex);
  670. if ((chip->mode & mode)) {
  671. mutex_unlock(&chip->open_mutex);
  672. return -EAGAIN;
  673. }
  674. if (chip->mode & CS4231_MODE_OPEN) {
  675. chip->mode |= mode;
  676. mutex_unlock(&chip->open_mutex);
  677. return 0;
  678. }
  679. /* ok. now enable and ack CODEC IRQ */
  680. spin_lock_irqsave(&chip->lock, flags);
  681. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  682. CS4231_RECORD_IRQ |
  683. CS4231_TIMER_IRQ);
  684. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  685. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  686. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  687. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  688. CS4231_RECORD_IRQ |
  689. CS4231_TIMER_IRQ);
  690. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  691. spin_unlock_irqrestore(&chip->lock, flags);
  692. chip->mode = mode;
  693. mutex_unlock(&chip->open_mutex);
  694. return 0;
  695. }
  696. static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
  697. {
  698. unsigned long flags;
  699. mutex_lock(&chip->open_mutex);
  700. chip->mode &= ~mode;
  701. if (chip->mode & CS4231_MODE_OPEN) {
  702. mutex_unlock(&chip->open_mutex);
  703. return;
  704. }
  705. snd_cs4231_calibrate_mute(chip, 1);
  706. /* disable IRQ */
  707. spin_lock_irqsave(&chip->lock, flags);
  708. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  709. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  710. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  711. /* now disable record & playback */
  712. if (chip->image[CS4231_IFACE_CTRL] &
  713. (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  714. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
  715. spin_unlock_irqrestore(&chip->lock, flags);
  716. snd_cs4231_mce_up(chip);
  717. spin_lock_irqsave(&chip->lock, flags);
  718. chip->image[CS4231_IFACE_CTRL] &=
  719. ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  720. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  721. snd_cs4231_out(chip, CS4231_IFACE_CTRL,
  722. chip->image[CS4231_IFACE_CTRL]);
  723. spin_unlock_irqrestore(&chip->lock, flags);
  724. snd_cs4231_mce_down(chip);
  725. spin_lock_irqsave(&chip->lock, flags);
  726. }
  727. /* clear IRQ again */
  728. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  729. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  730. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  731. spin_unlock_irqrestore(&chip->lock, flags);
  732. snd_cs4231_calibrate_mute(chip, 0);
  733. chip->mode = 0;
  734. mutex_unlock(&chip->open_mutex);
  735. }
  736. /*
  737. * timer open/close
  738. */
  739. static int snd_cs4231_timer_open(struct snd_timer *timer)
  740. {
  741. struct snd_cs4231 *chip = snd_timer_chip(timer);
  742. snd_cs4231_open(chip, CS4231_MODE_TIMER);
  743. return 0;
  744. }
  745. static int snd_cs4231_timer_close(struct snd_timer *timer)
  746. {
  747. struct snd_cs4231 *chip = snd_timer_chip(timer);
  748. snd_cs4231_close(chip, CS4231_MODE_TIMER);
  749. return 0;
  750. }
  751. static struct snd_timer_hardware snd_cs4231_timer_table = {
  752. .flags = SNDRV_TIMER_HW_AUTO,
  753. .resolution = 9945,
  754. .ticks = 65535,
  755. .open = snd_cs4231_timer_open,
  756. .close = snd_cs4231_timer_close,
  757. .c_resolution = snd_cs4231_timer_resolution,
  758. .start = snd_cs4231_timer_start,
  759. .stop = snd_cs4231_timer_stop,
  760. };
  761. /*
  762. * ok.. exported functions..
  763. */
  764. static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
  765. struct snd_pcm_hw_params *hw_params)
  766. {
  767. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  768. unsigned char new_pdfr;
  769. int err;
  770. err = snd_pcm_lib_malloc_pages(substream,
  771. params_buffer_bytes(hw_params));
  772. if (err < 0)
  773. return err;
  774. new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params),
  775. params_channels(hw_params)) |
  776. snd_cs4231_get_rate(params_rate(hw_params));
  777. snd_cs4231_playback_format(chip, hw_params, new_pdfr);
  778. return 0;
  779. }
  780. static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
  781. {
  782. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  783. struct snd_pcm_runtime *runtime = substream->runtime;
  784. unsigned long flags;
  785. int ret = 0;
  786. spin_lock_irqsave(&chip->lock, flags);
  787. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
  788. CS4231_PLAYBACK_PIO);
  789. if (WARN_ON(runtime->period_size > 0xffff + 1)) {
  790. ret = -EINVAL;
  791. goto out;
  792. }
  793. chip->p_periods_sent = 0;
  794. out:
  795. spin_unlock_irqrestore(&chip->lock, flags);
  796. return ret;
  797. }
  798. static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
  799. struct snd_pcm_hw_params *hw_params)
  800. {
  801. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  802. unsigned char new_cdfr;
  803. int err;
  804. err = snd_pcm_lib_malloc_pages(substream,
  805. params_buffer_bytes(hw_params));
  806. if (err < 0)
  807. return err;
  808. new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params),
  809. params_channels(hw_params)) |
  810. snd_cs4231_get_rate(params_rate(hw_params));
  811. snd_cs4231_capture_format(chip, hw_params, new_cdfr);
  812. return 0;
  813. }
  814. static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
  815. {
  816. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  817. unsigned long flags;
  818. spin_lock_irqsave(&chip->lock, flags);
  819. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
  820. CS4231_RECORD_PIO);
  821. chip->c_periods_sent = 0;
  822. spin_unlock_irqrestore(&chip->lock, flags);
  823. return 0;
  824. }
  825. static void snd_cs4231_overrange(struct snd_cs4231 *chip)
  826. {
  827. unsigned long flags;
  828. unsigned char res;
  829. spin_lock_irqsave(&chip->lock, flags);
  830. res = snd_cs4231_in(chip, CS4231_TEST_INIT);
  831. spin_unlock_irqrestore(&chip->lock, flags);
  832. /* detect overrange only above 0dB; may be user selectable? */
  833. if (res & (0x08 | 0x02))
  834. chip->capture_substream->runtime->overrange++;
  835. }
  836. static void snd_cs4231_play_callback(struct snd_cs4231 *chip)
  837. {
  838. if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) {
  839. snd_pcm_period_elapsed(chip->playback_substream);
  840. snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream,
  841. &chip->p_periods_sent);
  842. }
  843. }
  844. static void snd_cs4231_capture_callback(struct snd_cs4231 *chip)
  845. {
  846. if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) {
  847. snd_pcm_period_elapsed(chip->capture_substream);
  848. snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream,
  849. &chip->c_periods_sent);
  850. }
  851. }
  852. static snd_pcm_uframes_t snd_cs4231_playback_pointer(
  853. struct snd_pcm_substream *substream)
  854. {
  855. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  856. struct cs4231_dma_control *dma_cont = &chip->p_dma;
  857. size_t ptr;
  858. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
  859. return 0;
  860. ptr = dma_cont->address(dma_cont);
  861. if (ptr != 0)
  862. ptr -= substream->runtime->dma_addr;
  863. return bytes_to_frames(substream->runtime, ptr);
  864. }
  865. static snd_pcm_uframes_t snd_cs4231_capture_pointer(
  866. struct snd_pcm_substream *substream)
  867. {
  868. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  869. struct cs4231_dma_control *dma_cont = &chip->c_dma;
  870. size_t ptr;
  871. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
  872. return 0;
  873. ptr = dma_cont->address(dma_cont);
  874. if (ptr != 0)
  875. ptr -= substream->runtime->dma_addr;
  876. return bytes_to_frames(substream->runtime, ptr);
  877. }
  878. static int snd_cs4231_probe(struct snd_cs4231 *chip)
  879. {
  880. unsigned long flags;
  881. int i;
  882. int id = 0;
  883. int vers = 0;
  884. unsigned char *ptr;
  885. for (i = 0; i < 50; i++) {
  886. mb();
  887. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  888. msleep(2);
  889. else {
  890. spin_lock_irqsave(&chip->lock, flags);
  891. snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
  892. id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
  893. vers = snd_cs4231_in(chip, CS4231_VERSION);
  894. spin_unlock_irqrestore(&chip->lock, flags);
  895. if (id == 0x0a)
  896. break; /* this is valid value */
  897. }
  898. }
  899. snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id);
  900. if (id != 0x0a)
  901. return -ENODEV; /* no valid device found */
  902. spin_lock_irqsave(&chip->lock, flags);
  903. /* clear any pendings IRQ */
  904. __cs4231_readb(chip, CS4231U(chip, STATUS));
  905. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS));
  906. mb();
  907. spin_unlock_irqrestore(&chip->lock, flags);
  908. chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
  909. chip->image[CS4231_IFACE_CTRL] =
  910. chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA;
  911. chip->image[CS4231_ALT_FEATURE_1] = 0x80;
  912. chip->image[CS4231_ALT_FEATURE_2] = 0x01;
  913. if (vers & 0x20)
  914. chip->image[CS4231_ALT_FEATURE_2] |= 0x02;
  915. ptr = (unsigned char *) &chip->image;
  916. snd_cs4231_mce_down(chip);
  917. spin_lock_irqsave(&chip->lock, flags);
  918. for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
  919. snd_cs4231_out(chip, i, *ptr++);
  920. spin_unlock_irqrestore(&chip->lock, flags);
  921. snd_cs4231_mce_up(chip);
  922. snd_cs4231_mce_down(chip);
  923. mdelay(2);
  924. return 0; /* all things are ok.. */
  925. }
  926. static struct snd_pcm_hardware snd_cs4231_playback = {
  927. .info = SNDRV_PCM_INFO_MMAP |
  928. SNDRV_PCM_INFO_INTERLEAVED |
  929. SNDRV_PCM_INFO_MMAP_VALID |
  930. SNDRV_PCM_INFO_SYNC_START,
  931. .formats = SNDRV_PCM_FMTBIT_MU_LAW |
  932. SNDRV_PCM_FMTBIT_A_LAW |
  933. SNDRV_PCM_FMTBIT_IMA_ADPCM |
  934. SNDRV_PCM_FMTBIT_U8 |
  935. SNDRV_PCM_FMTBIT_S16_LE |
  936. SNDRV_PCM_FMTBIT_S16_BE,
  937. .rates = SNDRV_PCM_RATE_KNOT |
  938. SNDRV_PCM_RATE_8000_48000,
  939. .rate_min = 5510,
  940. .rate_max = 48000,
  941. .channels_min = 1,
  942. .channels_max = 2,
  943. .buffer_bytes_max = 32 * 1024,
  944. .period_bytes_min = 64,
  945. .period_bytes_max = 32 * 1024,
  946. .periods_min = 1,
  947. .periods_max = 1024,
  948. };
  949. static struct snd_pcm_hardware snd_cs4231_capture = {
  950. .info = SNDRV_PCM_INFO_MMAP |
  951. SNDRV_PCM_INFO_INTERLEAVED |
  952. SNDRV_PCM_INFO_MMAP_VALID |
  953. SNDRV_PCM_INFO_SYNC_START,
  954. .formats = SNDRV_PCM_FMTBIT_MU_LAW |
  955. SNDRV_PCM_FMTBIT_A_LAW |
  956. SNDRV_PCM_FMTBIT_IMA_ADPCM |
  957. SNDRV_PCM_FMTBIT_U8 |
  958. SNDRV_PCM_FMTBIT_S16_LE |
  959. SNDRV_PCM_FMTBIT_S16_BE,
  960. .rates = SNDRV_PCM_RATE_KNOT |
  961. SNDRV_PCM_RATE_8000_48000,
  962. .rate_min = 5510,
  963. .rate_max = 48000,
  964. .channels_min = 1,
  965. .channels_max = 2,
  966. .buffer_bytes_max = 32 * 1024,
  967. .period_bytes_min = 64,
  968. .period_bytes_max = 32 * 1024,
  969. .periods_min = 1,
  970. .periods_max = 1024,
  971. };
  972. static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
  973. {
  974. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  975. struct snd_pcm_runtime *runtime = substream->runtime;
  976. int err;
  977. runtime->hw = snd_cs4231_playback;
  978. err = snd_cs4231_open(chip, CS4231_MODE_PLAY);
  979. if (err < 0)
  980. return err;
  981. chip->playback_substream = substream;
  982. chip->p_periods_sent = 0;
  983. snd_pcm_set_sync(substream);
  984. snd_cs4231_xrate(runtime);
  985. return 0;
  986. }
  987. static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
  988. {
  989. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  990. struct snd_pcm_runtime *runtime = substream->runtime;
  991. int err;
  992. runtime->hw = snd_cs4231_capture;
  993. err = snd_cs4231_open(chip, CS4231_MODE_RECORD);
  994. if (err < 0)
  995. return err;
  996. chip->capture_substream = substream;
  997. chip->c_periods_sent = 0;
  998. snd_pcm_set_sync(substream);
  999. snd_cs4231_xrate(runtime);
  1000. return 0;
  1001. }
  1002. static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
  1003. {
  1004. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1005. snd_cs4231_close(chip, CS4231_MODE_PLAY);
  1006. chip->playback_substream = NULL;
  1007. return 0;
  1008. }
  1009. static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
  1010. {
  1011. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1012. snd_cs4231_close(chip, CS4231_MODE_RECORD);
  1013. chip->capture_substream = NULL;
  1014. return 0;
  1015. }
  1016. /* XXX We can do some power-management, in particular on EBUS using
  1017. * XXX the audio AUXIO register...
  1018. */
  1019. static struct snd_pcm_ops snd_cs4231_playback_ops = {
  1020. .open = snd_cs4231_playback_open,
  1021. .close = snd_cs4231_playback_close,
  1022. .ioctl = snd_pcm_lib_ioctl,
  1023. .hw_params = snd_cs4231_playback_hw_params,
  1024. .hw_free = snd_pcm_lib_free_pages,
  1025. .prepare = snd_cs4231_playback_prepare,
  1026. .trigger = snd_cs4231_trigger,
  1027. .pointer = snd_cs4231_playback_pointer,
  1028. };
  1029. static struct snd_pcm_ops snd_cs4231_capture_ops = {
  1030. .open = snd_cs4231_capture_open,
  1031. .close = snd_cs4231_capture_close,
  1032. .ioctl = snd_pcm_lib_ioctl,
  1033. .hw_params = snd_cs4231_capture_hw_params,
  1034. .hw_free = snd_pcm_lib_free_pages,
  1035. .prepare = snd_cs4231_capture_prepare,
  1036. .trigger = snd_cs4231_trigger,
  1037. .pointer = snd_cs4231_capture_pointer,
  1038. };
  1039. static int snd_cs4231_pcm(struct snd_card *card)
  1040. {
  1041. struct snd_cs4231 *chip = card->private_data;
  1042. struct snd_pcm *pcm;
  1043. int err;
  1044. err = snd_pcm_new(card, "CS4231", 0, 1, 1, &pcm);
  1045. if (err < 0)
  1046. return err;
  1047. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1048. &snd_cs4231_playback_ops);
  1049. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  1050. &snd_cs4231_capture_ops);
  1051. /* global setup */
  1052. pcm->private_data = chip;
  1053. pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
  1054. strcpy(pcm->name, "CS4231");
  1055. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1056. &chip->op->dev,
  1057. 64 * 1024, 128 * 1024);
  1058. chip->pcm = pcm;
  1059. return 0;
  1060. }
  1061. static int snd_cs4231_timer(struct snd_card *card)
  1062. {
  1063. struct snd_cs4231 *chip = card->private_data;
  1064. struct snd_timer *timer;
  1065. struct snd_timer_id tid;
  1066. int err;
  1067. /* Timer initialization */
  1068. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1069. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1070. tid.card = card->number;
  1071. tid.device = 0;
  1072. tid.subdevice = 0;
  1073. err = snd_timer_new(card, "CS4231", &tid, &timer);
  1074. if (err < 0)
  1075. return err;
  1076. strcpy(timer->name, "CS4231");
  1077. timer->private_data = chip;
  1078. timer->hw = snd_cs4231_timer_table;
  1079. chip->timer = timer;
  1080. return 0;
  1081. }
  1082. /*
  1083. * MIXER part
  1084. */
  1085. static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol,
  1086. struct snd_ctl_elem_info *uinfo)
  1087. {
  1088. static const char * const texts[4] = {
  1089. "Line", "CD", "Mic", "Mix"
  1090. };
  1091. return snd_ctl_enum_info(uinfo, 2, 4, texts);
  1092. }
  1093. static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol,
  1094. struct snd_ctl_elem_value *ucontrol)
  1095. {
  1096. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1097. unsigned long flags;
  1098. spin_lock_irqsave(&chip->lock, flags);
  1099. ucontrol->value.enumerated.item[0] =
  1100. (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1101. ucontrol->value.enumerated.item[1] =
  1102. (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1103. spin_unlock_irqrestore(&chip->lock, flags);
  1104. return 0;
  1105. }
  1106. static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol,
  1107. struct snd_ctl_elem_value *ucontrol)
  1108. {
  1109. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1110. unsigned long flags;
  1111. unsigned short left, right;
  1112. int change;
  1113. if (ucontrol->value.enumerated.item[0] > 3 ||
  1114. ucontrol->value.enumerated.item[1] > 3)
  1115. return -EINVAL;
  1116. left = ucontrol->value.enumerated.item[0] << 6;
  1117. right = ucontrol->value.enumerated.item[1] << 6;
  1118. spin_lock_irqsave(&chip->lock, flags);
  1119. left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
  1120. right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
  1121. change = left != chip->image[CS4231_LEFT_INPUT] ||
  1122. right != chip->image[CS4231_RIGHT_INPUT];
  1123. snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
  1124. snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
  1125. spin_unlock_irqrestore(&chip->lock, flags);
  1126. return change;
  1127. }
  1128. static int snd_cs4231_info_single(struct snd_kcontrol *kcontrol,
  1129. struct snd_ctl_elem_info *uinfo)
  1130. {
  1131. int mask = (kcontrol->private_value >> 16) & 0xff;
  1132. uinfo->type = (mask == 1) ?
  1133. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1134. uinfo->count = 1;
  1135. uinfo->value.integer.min = 0;
  1136. uinfo->value.integer.max = mask;
  1137. return 0;
  1138. }
  1139. static int snd_cs4231_get_single(struct snd_kcontrol *kcontrol,
  1140. struct snd_ctl_elem_value *ucontrol)
  1141. {
  1142. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1143. unsigned long flags;
  1144. int reg = kcontrol->private_value & 0xff;
  1145. int shift = (kcontrol->private_value >> 8) & 0xff;
  1146. int mask = (kcontrol->private_value >> 16) & 0xff;
  1147. int invert = (kcontrol->private_value >> 24) & 0xff;
  1148. spin_lock_irqsave(&chip->lock, flags);
  1149. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  1150. spin_unlock_irqrestore(&chip->lock, flags);
  1151. if (invert)
  1152. ucontrol->value.integer.value[0] =
  1153. (mask - ucontrol->value.integer.value[0]);
  1154. return 0;
  1155. }
  1156. static int snd_cs4231_put_single(struct snd_kcontrol *kcontrol,
  1157. struct snd_ctl_elem_value *ucontrol)
  1158. {
  1159. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1160. unsigned long flags;
  1161. int reg = kcontrol->private_value & 0xff;
  1162. int shift = (kcontrol->private_value >> 8) & 0xff;
  1163. int mask = (kcontrol->private_value >> 16) & 0xff;
  1164. int invert = (kcontrol->private_value >> 24) & 0xff;
  1165. int change;
  1166. unsigned short val;
  1167. val = (ucontrol->value.integer.value[0] & mask);
  1168. if (invert)
  1169. val = mask - val;
  1170. val <<= shift;
  1171. spin_lock_irqsave(&chip->lock, flags);
  1172. val = (chip->image[reg] & ~(mask << shift)) | val;
  1173. change = val != chip->image[reg];
  1174. snd_cs4231_out(chip, reg, val);
  1175. spin_unlock_irqrestore(&chip->lock, flags);
  1176. return change;
  1177. }
  1178. static int snd_cs4231_info_double(struct snd_kcontrol *kcontrol,
  1179. struct snd_ctl_elem_info *uinfo)
  1180. {
  1181. int mask = (kcontrol->private_value >> 24) & 0xff;
  1182. uinfo->type = mask == 1 ?
  1183. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1184. uinfo->count = 2;
  1185. uinfo->value.integer.min = 0;
  1186. uinfo->value.integer.max = mask;
  1187. return 0;
  1188. }
  1189. static int snd_cs4231_get_double(struct snd_kcontrol *kcontrol,
  1190. struct snd_ctl_elem_value *ucontrol)
  1191. {
  1192. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1193. unsigned long flags;
  1194. int left_reg = kcontrol->private_value & 0xff;
  1195. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1196. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1197. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1198. int mask = (kcontrol->private_value >> 24) & 0xff;
  1199. int invert = (kcontrol->private_value >> 22) & 1;
  1200. spin_lock_irqsave(&chip->lock, flags);
  1201. ucontrol->value.integer.value[0] =
  1202. (chip->image[left_reg] >> shift_left) & mask;
  1203. ucontrol->value.integer.value[1] =
  1204. (chip->image[right_reg] >> shift_right) & mask;
  1205. spin_unlock_irqrestore(&chip->lock, flags);
  1206. if (invert) {
  1207. ucontrol->value.integer.value[0] =
  1208. (mask - ucontrol->value.integer.value[0]);
  1209. ucontrol->value.integer.value[1] =
  1210. (mask - ucontrol->value.integer.value[1]);
  1211. }
  1212. return 0;
  1213. }
  1214. static int snd_cs4231_put_double(struct snd_kcontrol *kcontrol,
  1215. struct snd_ctl_elem_value *ucontrol)
  1216. {
  1217. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1218. unsigned long flags;
  1219. int left_reg = kcontrol->private_value & 0xff;
  1220. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1221. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1222. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1223. int mask = (kcontrol->private_value >> 24) & 0xff;
  1224. int invert = (kcontrol->private_value >> 22) & 1;
  1225. int change;
  1226. unsigned short val1, val2;
  1227. val1 = ucontrol->value.integer.value[0] & mask;
  1228. val2 = ucontrol->value.integer.value[1] & mask;
  1229. if (invert) {
  1230. val1 = mask - val1;
  1231. val2 = mask - val2;
  1232. }
  1233. val1 <<= shift_left;
  1234. val2 <<= shift_right;
  1235. spin_lock_irqsave(&chip->lock, flags);
  1236. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1237. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1238. change = val1 != chip->image[left_reg];
  1239. change |= val2 != chip->image[right_reg];
  1240. snd_cs4231_out(chip, left_reg, val1);
  1241. snd_cs4231_out(chip, right_reg, val2);
  1242. spin_unlock_irqrestore(&chip->lock, flags);
  1243. return change;
  1244. }
  1245. #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
  1246. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
  1247. .info = snd_cs4231_info_single, \
  1248. .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
  1249. .private_value = (reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24) }
  1250. #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, \
  1251. shift_right, mask, invert) \
  1252. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
  1253. .info = snd_cs4231_info_double, \
  1254. .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
  1255. .private_value = (left_reg) | ((right_reg) << 8) | ((shift_left) << 16) | \
  1256. ((shift_right) << 19) | ((mask) << 24) | ((invert) << 22) }
  1257. static struct snd_kcontrol_new snd_cs4231_controls[] = {
  1258. CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT,
  1259. CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
  1260. CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT,
  1261. CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
  1262. CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN,
  1263. CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
  1264. CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN,
  1265. CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
  1266. CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT,
  1267. CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1268. CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT,
  1269. CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
  1270. CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT,
  1271. CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1272. CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT,
  1273. CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
  1274. CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
  1275. CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
  1276. CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
  1277. CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
  1278. CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0,
  1279. 15, 0),
  1280. {
  1281. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1282. .name = "Capture Source",
  1283. .info = snd_cs4231_info_mux,
  1284. .get = snd_cs4231_get_mux,
  1285. .put = snd_cs4231_put_mux,
  1286. },
  1287. CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5,
  1288. 1, 0),
  1289. CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
  1290. CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1),
  1291. /* SPARC specific uses of XCTL{0,1} general purpose outputs. */
  1292. CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1),
  1293. CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1)
  1294. };
  1295. static int snd_cs4231_mixer(struct snd_card *card)
  1296. {
  1297. struct snd_cs4231 *chip = card->private_data;
  1298. int err, idx;
  1299. if (snd_BUG_ON(!chip || !chip->pcm))
  1300. return -EINVAL;
  1301. strcpy(card->mixername, chip->pcm->name);
  1302. for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
  1303. err = snd_ctl_add(card,
  1304. snd_ctl_new1(&snd_cs4231_controls[idx], chip));
  1305. if (err < 0)
  1306. return err;
  1307. }
  1308. return 0;
  1309. }
  1310. static int dev;
  1311. static int cs4231_attach_begin(struct platform_device *op,
  1312. struct snd_card **rcard)
  1313. {
  1314. struct snd_card *card;
  1315. struct snd_cs4231 *chip;
  1316. int err;
  1317. *rcard = NULL;
  1318. if (dev >= SNDRV_CARDS)
  1319. return -ENODEV;
  1320. if (!enable[dev]) {
  1321. dev++;
  1322. return -ENOENT;
  1323. }
  1324. err = snd_card_new(&op->dev, index[dev], id[dev], THIS_MODULE,
  1325. sizeof(struct snd_cs4231), &card);
  1326. if (err < 0)
  1327. return err;
  1328. strcpy(card->driver, "CS4231");
  1329. strcpy(card->shortname, "Sun CS4231");
  1330. chip = card->private_data;
  1331. chip->card = card;
  1332. *rcard = card;
  1333. return 0;
  1334. }
  1335. static int cs4231_attach_finish(struct snd_card *card)
  1336. {
  1337. struct snd_cs4231 *chip = card->private_data;
  1338. int err;
  1339. err = snd_cs4231_pcm(card);
  1340. if (err < 0)
  1341. goto out_err;
  1342. err = snd_cs4231_mixer(card);
  1343. if (err < 0)
  1344. goto out_err;
  1345. err = snd_cs4231_timer(card);
  1346. if (err < 0)
  1347. goto out_err;
  1348. err = snd_card_register(card);
  1349. if (err < 0)
  1350. goto out_err;
  1351. dev_set_drvdata(&chip->op->dev, chip);
  1352. dev++;
  1353. return 0;
  1354. out_err:
  1355. snd_card_free(card);
  1356. return err;
  1357. }
  1358. #ifdef SBUS_SUPPORT
  1359. static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id)
  1360. {
  1361. unsigned long flags;
  1362. unsigned char status;
  1363. u32 csr;
  1364. struct snd_cs4231 *chip = dev_id;
  1365. /*This is IRQ is not raised by the cs4231*/
  1366. if (!(__cs4231_readb(chip, CS4231U(chip, STATUS)) & CS4231_GLOBALIRQ))
  1367. return IRQ_NONE;
  1368. /* ACK the APC interrupt. */
  1369. csr = sbus_readl(chip->port + APCCSR);
  1370. sbus_writel(csr, chip->port + APCCSR);
  1371. if ((csr & APC_PDMA_READY) &&
  1372. (csr & APC_PLAY_INT) &&
  1373. (csr & APC_XINT_PNVA) &&
  1374. !(csr & APC_XINT_EMPT))
  1375. snd_cs4231_play_callback(chip);
  1376. if ((csr & APC_CDMA_READY) &&
  1377. (csr & APC_CAPT_INT) &&
  1378. (csr & APC_XINT_CNVA) &&
  1379. !(csr & APC_XINT_EMPT))
  1380. snd_cs4231_capture_callback(chip);
  1381. status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
  1382. if (status & CS4231_TIMER_IRQ) {
  1383. if (chip->timer)
  1384. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  1385. }
  1386. if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY))
  1387. snd_cs4231_overrange(chip);
  1388. /* ACK the CS4231 interrupt. */
  1389. spin_lock_irqsave(&chip->lock, flags);
  1390. snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
  1391. spin_unlock_irqrestore(&chip->lock, flags);
  1392. return IRQ_HANDLED;
  1393. }
  1394. /*
  1395. * SBUS DMA routines
  1396. */
  1397. static int sbus_dma_request(struct cs4231_dma_control *dma_cont,
  1398. dma_addr_t bus_addr, size_t len)
  1399. {
  1400. unsigned long flags;
  1401. u32 test, csr;
  1402. int err;
  1403. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1404. if (len >= (1 << 24))
  1405. return -EINVAL;
  1406. spin_lock_irqsave(&base->lock, flags);
  1407. csr = sbus_readl(base->regs + APCCSR);
  1408. err = -EINVAL;
  1409. test = APC_CDMA_READY;
  1410. if (base->dir == APC_PLAY)
  1411. test = APC_PDMA_READY;
  1412. if (!(csr & test))
  1413. goto out;
  1414. err = -EBUSY;
  1415. test = APC_XINT_CNVA;
  1416. if (base->dir == APC_PLAY)
  1417. test = APC_XINT_PNVA;
  1418. if (!(csr & test))
  1419. goto out;
  1420. err = 0;
  1421. sbus_writel(bus_addr, base->regs + base->dir + APCNVA);
  1422. sbus_writel(len, base->regs + base->dir + APCNC);
  1423. out:
  1424. spin_unlock_irqrestore(&base->lock, flags);
  1425. return err;
  1426. }
  1427. static void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d)
  1428. {
  1429. unsigned long flags;
  1430. u32 csr, test;
  1431. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1432. spin_lock_irqsave(&base->lock, flags);
  1433. csr = sbus_readl(base->regs + APCCSR);
  1434. test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
  1435. APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL |
  1436. APC_XINT_PENA;
  1437. if (base->dir == APC_RECORD)
  1438. test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
  1439. APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL;
  1440. csr |= test;
  1441. sbus_writel(csr, base->regs + APCCSR);
  1442. spin_unlock_irqrestore(&base->lock, flags);
  1443. }
  1444. static void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
  1445. {
  1446. unsigned long flags;
  1447. u32 csr, shift;
  1448. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1449. spin_lock_irqsave(&base->lock, flags);
  1450. if (!on) {
  1451. sbus_writel(0, base->regs + base->dir + APCNC);
  1452. sbus_writel(0, base->regs + base->dir + APCNVA);
  1453. if (base->dir == APC_PLAY) {
  1454. sbus_writel(0, base->regs + base->dir + APCC);
  1455. sbus_writel(0, base->regs + base->dir + APCVA);
  1456. }
  1457. udelay(1200);
  1458. }
  1459. csr = sbus_readl(base->regs + APCCSR);
  1460. shift = 0;
  1461. if (base->dir == APC_PLAY)
  1462. shift = 1;
  1463. if (on)
  1464. csr &= ~(APC_CPAUSE << shift);
  1465. else
  1466. csr |= (APC_CPAUSE << shift);
  1467. sbus_writel(csr, base->regs + APCCSR);
  1468. if (on)
  1469. csr |= (APC_CDMA_READY << shift);
  1470. else
  1471. csr &= ~(APC_CDMA_READY << shift);
  1472. sbus_writel(csr, base->regs + APCCSR);
  1473. spin_unlock_irqrestore(&base->lock, flags);
  1474. }
  1475. static unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont)
  1476. {
  1477. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1478. return sbus_readl(base->regs + base->dir + APCVA);
  1479. }
  1480. /*
  1481. * Init and exit routines
  1482. */
  1483. static int snd_cs4231_sbus_free(struct snd_cs4231 *chip)
  1484. {
  1485. struct platform_device *op = chip->op;
  1486. if (chip->irq[0])
  1487. free_irq(chip->irq[0], chip);
  1488. if (chip->port)
  1489. of_iounmap(&op->resource[0], chip->port, chip->regs_size);
  1490. return 0;
  1491. }
  1492. static int snd_cs4231_sbus_dev_free(struct snd_device *device)
  1493. {
  1494. struct snd_cs4231 *cp = device->device_data;
  1495. return snd_cs4231_sbus_free(cp);
  1496. }
  1497. static struct snd_device_ops snd_cs4231_sbus_dev_ops = {
  1498. .dev_free = snd_cs4231_sbus_dev_free,
  1499. };
  1500. static int snd_cs4231_sbus_create(struct snd_card *card,
  1501. struct platform_device *op,
  1502. int dev)
  1503. {
  1504. struct snd_cs4231 *chip = card->private_data;
  1505. int err;
  1506. spin_lock_init(&chip->lock);
  1507. spin_lock_init(&chip->c_dma.sbus_info.lock);
  1508. spin_lock_init(&chip->p_dma.sbus_info.lock);
  1509. mutex_init(&chip->mce_mutex);
  1510. mutex_init(&chip->open_mutex);
  1511. chip->op = op;
  1512. chip->regs_size = resource_size(&op->resource[0]);
  1513. memcpy(&chip->image, &snd_cs4231_original_image,
  1514. sizeof(snd_cs4231_original_image));
  1515. chip->port = of_ioremap(&op->resource[0], 0,
  1516. chip->regs_size, "cs4231");
  1517. if (!chip->port) {
  1518. snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
  1519. return -EIO;
  1520. }
  1521. chip->c_dma.sbus_info.regs = chip->port;
  1522. chip->p_dma.sbus_info.regs = chip->port;
  1523. chip->c_dma.sbus_info.dir = APC_RECORD;
  1524. chip->p_dma.sbus_info.dir = APC_PLAY;
  1525. chip->p_dma.prepare = sbus_dma_prepare;
  1526. chip->p_dma.enable = sbus_dma_enable;
  1527. chip->p_dma.request = sbus_dma_request;
  1528. chip->p_dma.address = sbus_dma_addr;
  1529. chip->c_dma.prepare = sbus_dma_prepare;
  1530. chip->c_dma.enable = sbus_dma_enable;
  1531. chip->c_dma.request = sbus_dma_request;
  1532. chip->c_dma.address = sbus_dma_addr;
  1533. if (request_irq(op->archdata.irqs[0], snd_cs4231_sbus_interrupt,
  1534. IRQF_SHARED, "cs4231", chip)) {
  1535. snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %d\n",
  1536. dev, op->archdata.irqs[0]);
  1537. snd_cs4231_sbus_free(chip);
  1538. return -EBUSY;
  1539. }
  1540. chip->irq[0] = op->archdata.irqs[0];
  1541. if (snd_cs4231_probe(chip) < 0) {
  1542. snd_cs4231_sbus_free(chip);
  1543. return -ENODEV;
  1544. }
  1545. snd_cs4231_init(chip);
  1546. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  1547. chip, &snd_cs4231_sbus_dev_ops)) < 0) {
  1548. snd_cs4231_sbus_free(chip);
  1549. return err;
  1550. }
  1551. return 0;
  1552. }
  1553. static int cs4231_sbus_probe(struct platform_device *op)
  1554. {
  1555. struct resource *rp = &op->resource[0];
  1556. struct snd_card *card;
  1557. int err;
  1558. err = cs4231_attach_begin(op, &card);
  1559. if (err)
  1560. return err;
  1561. sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
  1562. card->shortname,
  1563. rp->flags & 0xffL,
  1564. (unsigned long long)rp->start,
  1565. op->archdata.irqs[0]);
  1566. err = snd_cs4231_sbus_create(card, op, dev);
  1567. if (err < 0) {
  1568. snd_card_free(card);
  1569. return err;
  1570. }
  1571. return cs4231_attach_finish(card);
  1572. }
  1573. #endif
  1574. #ifdef EBUS_SUPPORT
  1575. static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event,
  1576. void *cookie)
  1577. {
  1578. struct snd_cs4231 *chip = cookie;
  1579. snd_cs4231_play_callback(chip);
  1580. }
  1581. static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p,
  1582. int event, void *cookie)
  1583. {
  1584. struct snd_cs4231 *chip = cookie;
  1585. snd_cs4231_capture_callback(chip);
  1586. }
  1587. /*
  1588. * EBUS DMA wrappers
  1589. */
  1590. static int _ebus_dma_request(struct cs4231_dma_control *dma_cont,
  1591. dma_addr_t bus_addr, size_t len)
  1592. {
  1593. return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len);
  1594. }
  1595. static void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
  1596. {
  1597. ebus_dma_enable(&dma_cont->ebus_info, on);
  1598. }
  1599. static void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir)
  1600. {
  1601. ebus_dma_prepare(&dma_cont->ebus_info, dir);
  1602. }
  1603. static unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont)
  1604. {
  1605. return ebus_dma_addr(&dma_cont->ebus_info);
  1606. }
  1607. /*
  1608. * Init and exit routines
  1609. */
  1610. static int snd_cs4231_ebus_free(struct snd_cs4231 *chip)
  1611. {
  1612. struct platform_device *op = chip->op;
  1613. if (chip->c_dma.ebus_info.regs) {
  1614. ebus_dma_unregister(&chip->c_dma.ebus_info);
  1615. of_iounmap(&op->resource[2], chip->c_dma.ebus_info.regs, 0x10);
  1616. }
  1617. if (chip->p_dma.ebus_info.regs) {
  1618. ebus_dma_unregister(&chip->p_dma.ebus_info);
  1619. of_iounmap(&op->resource[1], chip->p_dma.ebus_info.regs, 0x10);
  1620. }
  1621. if (chip->port)
  1622. of_iounmap(&op->resource[0], chip->port, 0x10);
  1623. return 0;
  1624. }
  1625. static int snd_cs4231_ebus_dev_free(struct snd_device *device)
  1626. {
  1627. struct snd_cs4231 *cp = device->device_data;
  1628. return snd_cs4231_ebus_free(cp);
  1629. }
  1630. static struct snd_device_ops snd_cs4231_ebus_dev_ops = {
  1631. .dev_free = snd_cs4231_ebus_dev_free,
  1632. };
  1633. static int snd_cs4231_ebus_create(struct snd_card *card,
  1634. struct platform_device *op,
  1635. int dev)
  1636. {
  1637. struct snd_cs4231 *chip = card->private_data;
  1638. int err;
  1639. spin_lock_init(&chip->lock);
  1640. spin_lock_init(&chip->c_dma.ebus_info.lock);
  1641. spin_lock_init(&chip->p_dma.ebus_info.lock);
  1642. mutex_init(&chip->mce_mutex);
  1643. mutex_init(&chip->open_mutex);
  1644. chip->flags |= CS4231_FLAG_EBUS;
  1645. chip->op = op;
  1646. memcpy(&chip->image, &snd_cs4231_original_image,
  1647. sizeof(snd_cs4231_original_image));
  1648. strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)");
  1649. chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
  1650. chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback;
  1651. chip->c_dma.ebus_info.client_cookie = chip;
  1652. chip->c_dma.ebus_info.irq = op->archdata.irqs[0];
  1653. strcpy(chip->p_dma.ebus_info.name, "cs4231(play)");
  1654. chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
  1655. chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback;
  1656. chip->p_dma.ebus_info.client_cookie = chip;
  1657. chip->p_dma.ebus_info.irq = op->archdata.irqs[1];
  1658. chip->p_dma.prepare = _ebus_dma_prepare;
  1659. chip->p_dma.enable = _ebus_dma_enable;
  1660. chip->p_dma.request = _ebus_dma_request;
  1661. chip->p_dma.address = _ebus_dma_addr;
  1662. chip->c_dma.prepare = _ebus_dma_prepare;
  1663. chip->c_dma.enable = _ebus_dma_enable;
  1664. chip->c_dma.request = _ebus_dma_request;
  1665. chip->c_dma.address = _ebus_dma_addr;
  1666. chip->port = of_ioremap(&op->resource[0], 0, 0x10, "cs4231");
  1667. chip->p_dma.ebus_info.regs =
  1668. of_ioremap(&op->resource[1], 0, 0x10, "cs4231_pdma");
  1669. chip->c_dma.ebus_info.regs =
  1670. of_ioremap(&op->resource[2], 0, 0x10, "cs4231_cdma");
  1671. if (!chip->port || !chip->p_dma.ebus_info.regs ||
  1672. !chip->c_dma.ebus_info.regs) {
  1673. snd_cs4231_ebus_free(chip);
  1674. snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
  1675. return -EIO;
  1676. }
  1677. if (ebus_dma_register(&chip->c_dma.ebus_info)) {
  1678. snd_cs4231_ebus_free(chip);
  1679. snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n",
  1680. dev);
  1681. return -EBUSY;
  1682. }
  1683. if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) {
  1684. snd_cs4231_ebus_free(chip);
  1685. snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n",
  1686. dev);
  1687. return -EBUSY;
  1688. }
  1689. if (ebus_dma_register(&chip->p_dma.ebus_info)) {
  1690. snd_cs4231_ebus_free(chip);
  1691. snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n",
  1692. dev);
  1693. return -EBUSY;
  1694. }
  1695. if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) {
  1696. snd_cs4231_ebus_free(chip);
  1697. snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
  1698. return -EBUSY;
  1699. }
  1700. if (snd_cs4231_probe(chip) < 0) {
  1701. snd_cs4231_ebus_free(chip);
  1702. return -ENODEV;
  1703. }
  1704. snd_cs4231_init(chip);
  1705. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  1706. chip, &snd_cs4231_ebus_dev_ops)) < 0) {
  1707. snd_cs4231_ebus_free(chip);
  1708. return err;
  1709. }
  1710. return 0;
  1711. }
  1712. static int cs4231_ebus_probe(struct platform_device *op)
  1713. {
  1714. struct snd_card *card;
  1715. int err;
  1716. err = cs4231_attach_begin(op, &card);
  1717. if (err)
  1718. return err;
  1719. sprintf(card->longname, "%s at 0x%llx, irq %d",
  1720. card->shortname,
  1721. op->resource[0].start,
  1722. op->archdata.irqs[0]);
  1723. err = snd_cs4231_ebus_create(card, op, dev);
  1724. if (err < 0) {
  1725. snd_card_free(card);
  1726. return err;
  1727. }
  1728. return cs4231_attach_finish(card);
  1729. }
  1730. #endif
  1731. static int cs4231_probe(struct platform_device *op)
  1732. {
  1733. #ifdef EBUS_SUPPORT
  1734. if (!strcmp(op->dev.of_node->parent->name, "ebus"))
  1735. return cs4231_ebus_probe(op);
  1736. #endif
  1737. #ifdef SBUS_SUPPORT
  1738. if (!strcmp(op->dev.of_node->parent->name, "sbus") ||
  1739. !strcmp(op->dev.of_node->parent->name, "sbi"))
  1740. return cs4231_sbus_probe(op);
  1741. #endif
  1742. return -ENODEV;
  1743. }
  1744. static int cs4231_remove(struct platform_device *op)
  1745. {
  1746. struct snd_cs4231 *chip = dev_get_drvdata(&op->dev);
  1747. snd_card_free(chip->card);
  1748. return 0;
  1749. }
  1750. static const struct of_device_id cs4231_match[] = {
  1751. {
  1752. .name = "SUNW,CS4231",
  1753. },
  1754. {
  1755. .name = "audio",
  1756. .compatible = "SUNW,CS4231",
  1757. },
  1758. {},
  1759. };
  1760. MODULE_DEVICE_TABLE(of, cs4231_match);
  1761. static struct platform_driver cs4231_driver = {
  1762. .driver = {
  1763. .name = "audio",
  1764. .of_match_table = cs4231_match,
  1765. },
  1766. .probe = cs4231_probe,
  1767. .remove = cs4231_remove,
  1768. };
  1769. module_platform_driver(cs4231_driver);