intel-pt.c 54 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197
  1. /*
  2. * intel_pt.c: Intel Processor Trace support
  3. * Copyright (c) 2013-2015, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. */
  15. #include <stdio.h>
  16. #include <stdbool.h>
  17. #include <errno.h>
  18. #include <linux/kernel.h>
  19. #include <linux/types.h>
  20. #include "../perf.h"
  21. #include "session.h"
  22. #include "machine.h"
  23. #include "sort.h"
  24. #include "tool.h"
  25. #include "event.h"
  26. #include "evlist.h"
  27. #include "evsel.h"
  28. #include "map.h"
  29. #include "color.h"
  30. #include "util.h"
  31. #include "thread.h"
  32. #include "thread-stack.h"
  33. #include "symbol.h"
  34. #include "callchain.h"
  35. #include "dso.h"
  36. #include "debug.h"
  37. #include "auxtrace.h"
  38. #include "tsc.h"
  39. #include "intel-pt.h"
  40. #include "intel-pt-decoder/intel-pt-log.h"
  41. #include "intel-pt-decoder/intel-pt-decoder.h"
  42. #include "intel-pt-decoder/intel-pt-insn-decoder.h"
  43. #include "intel-pt-decoder/intel-pt-pkt-decoder.h"
  44. #define MAX_TIMESTAMP (~0ULL)
  45. struct intel_pt {
  46. struct auxtrace auxtrace;
  47. struct auxtrace_queues queues;
  48. struct auxtrace_heap heap;
  49. u32 auxtrace_type;
  50. struct perf_session *session;
  51. struct machine *machine;
  52. struct perf_evsel *switch_evsel;
  53. struct thread *unknown_thread;
  54. bool timeless_decoding;
  55. bool sampling_mode;
  56. bool snapshot_mode;
  57. bool per_cpu_mmaps;
  58. bool have_tsc;
  59. bool data_queued;
  60. bool est_tsc;
  61. bool sync_switch;
  62. bool mispred_all;
  63. int have_sched_switch;
  64. u32 pmu_type;
  65. u64 kernel_start;
  66. u64 switch_ip;
  67. u64 ptss_ip;
  68. struct perf_tsc_conversion tc;
  69. bool cap_user_time_zero;
  70. struct itrace_synth_opts synth_opts;
  71. bool sample_instructions;
  72. u64 instructions_sample_type;
  73. u64 instructions_sample_period;
  74. u64 instructions_id;
  75. bool sample_branches;
  76. u32 branches_filter;
  77. u64 branches_sample_type;
  78. u64 branches_id;
  79. bool sample_transactions;
  80. u64 transactions_sample_type;
  81. u64 transactions_id;
  82. bool synth_needs_swap;
  83. u64 tsc_bit;
  84. u64 mtc_bit;
  85. u64 mtc_freq_bits;
  86. u32 tsc_ctc_ratio_n;
  87. u32 tsc_ctc_ratio_d;
  88. u64 cyc_bit;
  89. u64 noretcomp_bit;
  90. unsigned max_non_turbo_ratio;
  91. };
  92. enum switch_state {
  93. INTEL_PT_SS_NOT_TRACING,
  94. INTEL_PT_SS_UNKNOWN,
  95. INTEL_PT_SS_TRACING,
  96. INTEL_PT_SS_EXPECTING_SWITCH_EVENT,
  97. INTEL_PT_SS_EXPECTING_SWITCH_IP,
  98. };
  99. struct intel_pt_queue {
  100. struct intel_pt *pt;
  101. unsigned int queue_nr;
  102. struct auxtrace_buffer *buffer;
  103. void *decoder;
  104. const struct intel_pt_state *state;
  105. struct ip_callchain *chain;
  106. struct branch_stack *last_branch;
  107. struct branch_stack *last_branch_rb;
  108. size_t last_branch_pos;
  109. union perf_event *event_buf;
  110. bool on_heap;
  111. bool stop;
  112. bool step_through_buffers;
  113. bool use_buffer_pid_tid;
  114. bool sync_switch;
  115. pid_t pid, tid;
  116. int cpu;
  117. int switch_state;
  118. pid_t next_tid;
  119. struct thread *thread;
  120. bool exclude_kernel;
  121. bool have_sample;
  122. u64 time;
  123. u64 timestamp;
  124. u32 flags;
  125. u16 insn_len;
  126. u64 last_insn_cnt;
  127. };
  128. static void intel_pt_dump(struct intel_pt *pt __maybe_unused,
  129. unsigned char *buf, size_t len)
  130. {
  131. struct intel_pt_pkt packet;
  132. size_t pos = 0;
  133. int ret, pkt_len, i;
  134. char desc[INTEL_PT_PKT_DESC_MAX];
  135. const char *color = PERF_COLOR_BLUE;
  136. color_fprintf(stdout, color,
  137. ". ... Intel Processor Trace data: size %zu bytes\n",
  138. len);
  139. while (len) {
  140. ret = intel_pt_get_packet(buf, len, &packet);
  141. if (ret > 0)
  142. pkt_len = ret;
  143. else
  144. pkt_len = 1;
  145. printf(".");
  146. color_fprintf(stdout, color, " %08x: ", pos);
  147. for (i = 0; i < pkt_len; i++)
  148. color_fprintf(stdout, color, " %02x", buf[i]);
  149. for (; i < 16; i++)
  150. color_fprintf(stdout, color, " ");
  151. if (ret > 0) {
  152. ret = intel_pt_pkt_desc(&packet, desc,
  153. INTEL_PT_PKT_DESC_MAX);
  154. if (ret > 0)
  155. color_fprintf(stdout, color, " %s\n", desc);
  156. } else {
  157. color_fprintf(stdout, color, " Bad packet!\n");
  158. }
  159. pos += pkt_len;
  160. buf += pkt_len;
  161. len -= pkt_len;
  162. }
  163. }
  164. static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf,
  165. size_t len)
  166. {
  167. printf(".\n");
  168. intel_pt_dump(pt, buf, len);
  169. }
  170. static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a,
  171. struct auxtrace_buffer *b)
  172. {
  173. bool consecutive = false;
  174. void *start;
  175. start = intel_pt_find_overlap(a->data, a->size, b->data, b->size,
  176. pt->have_tsc, &consecutive);
  177. if (!start)
  178. return -EINVAL;
  179. b->use_size = b->data + b->size - start;
  180. b->use_data = start;
  181. if (b->use_size && consecutive)
  182. b->consecutive = true;
  183. return 0;
  184. }
  185. static void intel_pt_use_buffer_pid_tid(struct intel_pt_queue *ptq,
  186. struct auxtrace_queue *queue,
  187. struct auxtrace_buffer *buffer)
  188. {
  189. if (queue->cpu == -1 && buffer->cpu != -1)
  190. ptq->cpu = buffer->cpu;
  191. ptq->pid = buffer->pid;
  192. ptq->tid = buffer->tid;
  193. intel_pt_log("queue %u cpu %d pid %d tid %d\n",
  194. ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  195. thread__zput(ptq->thread);
  196. if (ptq->tid != -1) {
  197. if (ptq->pid != -1)
  198. ptq->thread = machine__findnew_thread(ptq->pt->machine,
  199. ptq->pid,
  200. ptq->tid);
  201. else
  202. ptq->thread = machine__find_thread(ptq->pt->machine, -1,
  203. ptq->tid);
  204. }
  205. }
  206. /* This function assumes data is processed sequentially only */
  207. static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data)
  208. {
  209. struct intel_pt_queue *ptq = data;
  210. struct auxtrace_buffer *buffer = ptq->buffer, *old_buffer = buffer;
  211. struct auxtrace_queue *queue;
  212. if (ptq->stop) {
  213. b->len = 0;
  214. return 0;
  215. }
  216. queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
  217. next:
  218. buffer = auxtrace_buffer__next(queue, buffer);
  219. if (!buffer) {
  220. if (old_buffer)
  221. auxtrace_buffer__drop_data(old_buffer);
  222. b->len = 0;
  223. return 0;
  224. }
  225. ptq->buffer = buffer;
  226. if (!buffer->data) {
  227. int fd = perf_data_file__fd(ptq->pt->session->file);
  228. buffer->data = auxtrace_buffer__get_data(buffer, fd);
  229. if (!buffer->data)
  230. return -ENOMEM;
  231. }
  232. if (ptq->pt->snapshot_mode && !buffer->consecutive && old_buffer &&
  233. intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer))
  234. return -ENOMEM;
  235. if (buffer->use_data) {
  236. b->len = buffer->use_size;
  237. b->buf = buffer->use_data;
  238. } else {
  239. b->len = buffer->size;
  240. b->buf = buffer->data;
  241. }
  242. b->ref_timestamp = buffer->reference;
  243. /*
  244. * If in snapshot mode and the buffer has no usable data, get next
  245. * buffer and again check overlap against old_buffer.
  246. */
  247. if (ptq->pt->snapshot_mode && !b->len)
  248. goto next;
  249. if (old_buffer)
  250. auxtrace_buffer__drop_data(old_buffer);
  251. if (!old_buffer || ptq->pt->sampling_mode || (ptq->pt->snapshot_mode &&
  252. !buffer->consecutive)) {
  253. b->consecutive = false;
  254. b->trace_nr = buffer->buffer_nr + 1;
  255. } else {
  256. b->consecutive = true;
  257. }
  258. if (ptq->use_buffer_pid_tid && (ptq->pid != buffer->pid ||
  259. ptq->tid != buffer->tid))
  260. intel_pt_use_buffer_pid_tid(ptq, queue, buffer);
  261. if (ptq->step_through_buffers)
  262. ptq->stop = true;
  263. if (!b->len)
  264. return intel_pt_get_trace(b, data);
  265. return 0;
  266. }
  267. struct intel_pt_cache_entry {
  268. struct auxtrace_cache_entry entry;
  269. u64 insn_cnt;
  270. u64 byte_cnt;
  271. enum intel_pt_insn_op op;
  272. enum intel_pt_insn_branch branch;
  273. int length;
  274. int32_t rel;
  275. };
  276. static int intel_pt_config_div(const char *var, const char *value, void *data)
  277. {
  278. int *d = data;
  279. long val;
  280. if (!strcmp(var, "intel-pt.cache-divisor")) {
  281. val = strtol(value, NULL, 0);
  282. if (val > 0 && val <= INT_MAX)
  283. *d = val;
  284. }
  285. return 0;
  286. }
  287. static int intel_pt_cache_divisor(void)
  288. {
  289. static int d;
  290. if (d)
  291. return d;
  292. perf_config(intel_pt_config_div, &d);
  293. if (!d)
  294. d = 64;
  295. return d;
  296. }
  297. static unsigned int intel_pt_cache_size(struct dso *dso,
  298. struct machine *machine)
  299. {
  300. off_t size;
  301. size = dso__data_size(dso, machine);
  302. size /= intel_pt_cache_divisor();
  303. if (size < 1000)
  304. return 10;
  305. if (size > (1 << 21))
  306. return 21;
  307. return 32 - __builtin_clz(size);
  308. }
  309. static struct auxtrace_cache *intel_pt_cache(struct dso *dso,
  310. struct machine *machine)
  311. {
  312. struct auxtrace_cache *c;
  313. unsigned int bits;
  314. if (dso->auxtrace_cache)
  315. return dso->auxtrace_cache;
  316. bits = intel_pt_cache_size(dso, machine);
  317. /* Ignoring cache creation failure */
  318. c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200);
  319. dso->auxtrace_cache = c;
  320. return c;
  321. }
  322. static int intel_pt_cache_add(struct dso *dso, struct machine *machine,
  323. u64 offset, u64 insn_cnt, u64 byte_cnt,
  324. struct intel_pt_insn *intel_pt_insn)
  325. {
  326. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  327. struct intel_pt_cache_entry *e;
  328. int err;
  329. if (!c)
  330. return -ENOMEM;
  331. e = auxtrace_cache__alloc_entry(c);
  332. if (!e)
  333. return -ENOMEM;
  334. e->insn_cnt = insn_cnt;
  335. e->byte_cnt = byte_cnt;
  336. e->op = intel_pt_insn->op;
  337. e->branch = intel_pt_insn->branch;
  338. e->length = intel_pt_insn->length;
  339. e->rel = intel_pt_insn->rel;
  340. err = auxtrace_cache__add(c, offset, &e->entry);
  341. if (err)
  342. auxtrace_cache__free_entry(c, e);
  343. return err;
  344. }
  345. static struct intel_pt_cache_entry *
  346. intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset)
  347. {
  348. struct auxtrace_cache *c = intel_pt_cache(dso, machine);
  349. if (!c)
  350. return NULL;
  351. return auxtrace_cache__lookup(dso->auxtrace_cache, offset);
  352. }
  353. static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn,
  354. uint64_t *insn_cnt_ptr, uint64_t *ip,
  355. uint64_t to_ip, uint64_t max_insn_cnt,
  356. void *data)
  357. {
  358. struct intel_pt_queue *ptq = data;
  359. struct machine *machine = ptq->pt->machine;
  360. struct thread *thread;
  361. struct addr_location al;
  362. unsigned char buf[1024];
  363. size_t bufsz;
  364. ssize_t len;
  365. int x86_64;
  366. u8 cpumode;
  367. u64 offset, start_offset, start_ip;
  368. u64 insn_cnt = 0;
  369. bool one_map = true;
  370. if (to_ip && *ip == to_ip)
  371. goto out_no_cache;
  372. bufsz = intel_pt_insn_max_size();
  373. if (*ip >= ptq->pt->kernel_start)
  374. cpumode = PERF_RECORD_MISC_KERNEL;
  375. else
  376. cpumode = PERF_RECORD_MISC_USER;
  377. thread = ptq->thread;
  378. if (!thread) {
  379. if (cpumode != PERF_RECORD_MISC_KERNEL)
  380. return -EINVAL;
  381. thread = ptq->pt->unknown_thread;
  382. }
  383. while (1) {
  384. thread__find_addr_map(thread, cpumode, MAP__FUNCTION, *ip, &al);
  385. if (!al.map || !al.map->dso)
  386. return -EINVAL;
  387. if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR &&
  388. dso__data_status_seen(al.map->dso,
  389. DSO_DATA_STATUS_SEEN_ITRACE))
  390. return -ENOENT;
  391. offset = al.map->map_ip(al.map, *ip);
  392. if (!to_ip && one_map) {
  393. struct intel_pt_cache_entry *e;
  394. e = intel_pt_cache_lookup(al.map->dso, machine, offset);
  395. if (e &&
  396. (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) {
  397. *insn_cnt_ptr = e->insn_cnt;
  398. *ip += e->byte_cnt;
  399. intel_pt_insn->op = e->op;
  400. intel_pt_insn->branch = e->branch;
  401. intel_pt_insn->length = e->length;
  402. intel_pt_insn->rel = e->rel;
  403. intel_pt_log_insn_no_data(intel_pt_insn, *ip);
  404. return 0;
  405. }
  406. }
  407. start_offset = offset;
  408. start_ip = *ip;
  409. /* Load maps to ensure dso->is_64_bit has been updated */
  410. map__load(al.map, machine->symbol_filter);
  411. x86_64 = al.map->dso->is_64_bit;
  412. while (1) {
  413. len = dso__data_read_offset(al.map->dso, machine,
  414. offset, buf, bufsz);
  415. if (len <= 0)
  416. return -EINVAL;
  417. if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn))
  418. return -EINVAL;
  419. intel_pt_log_insn(intel_pt_insn, *ip);
  420. insn_cnt += 1;
  421. if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH)
  422. goto out;
  423. if (max_insn_cnt && insn_cnt >= max_insn_cnt)
  424. goto out_no_cache;
  425. *ip += intel_pt_insn->length;
  426. if (to_ip && *ip == to_ip)
  427. goto out_no_cache;
  428. if (*ip >= al.map->end)
  429. break;
  430. offset += intel_pt_insn->length;
  431. }
  432. one_map = false;
  433. }
  434. out:
  435. *insn_cnt_ptr = insn_cnt;
  436. if (!one_map)
  437. goto out_no_cache;
  438. /*
  439. * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate
  440. * entries.
  441. */
  442. if (to_ip) {
  443. struct intel_pt_cache_entry *e;
  444. e = intel_pt_cache_lookup(al.map->dso, machine, start_offset);
  445. if (e)
  446. return 0;
  447. }
  448. /* Ignore cache errors */
  449. intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt,
  450. *ip - start_ip, intel_pt_insn);
  451. return 0;
  452. out_no_cache:
  453. *insn_cnt_ptr = insn_cnt;
  454. return 0;
  455. }
  456. static bool intel_pt_get_config(struct intel_pt *pt,
  457. struct perf_event_attr *attr, u64 *config)
  458. {
  459. if (attr->type == pt->pmu_type) {
  460. if (config)
  461. *config = attr->config;
  462. return true;
  463. }
  464. return false;
  465. }
  466. static bool intel_pt_exclude_kernel(struct intel_pt *pt)
  467. {
  468. struct perf_evsel *evsel;
  469. evlist__for_each(pt->session->evlist, evsel) {
  470. if (intel_pt_get_config(pt, &evsel->attr, NULL) &&
  471. !evsel->attr.exclude_kernel)
  472. return false;
  473. }
  474. return true;
  475. }
  476. static bool intel_pt_return_compression(struct intel_pt *pt)
  477. {
  478. struct perf_evsel *evsel;
  479. u64 config;
  480. if (!pt->noretcomp_bit)
  481. return true;
  482. evlist__for_each(pt->session->evlist, evsel) {
  483. if (intel_pt_get_config(pt, &evsel->attr, &config) &&
  484. (config & pt->noretcomp_bit))
  485. return false;
  486. }
  487. return true;
  488. }
  489. static unsigned int intel_pt_mtc_period(struct intel_pt *pt)
  490. {
  491. struct perf_evsel *evsel;
  492. unsigned int shift;
  493. u64 config;
  494. if (!pt->mtc_freq_bits)
  495. return 0;
  496. for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++)
  497. config >>= 1;
  498. evlist__for_each(pt->session->evlist, evsel) {
  499. if (intel_pt_get_config(pt, &evsel->attr, &config))
  500. return (config & pt->mtc_freq_bits) >> shift;
  501. }
  502. return 0;
  503. }
  504. static bool intel_pt_timeless_decoding(struct intel_pt *pt)
  505. {
  506. struct perf_evsel *evsel;
  507. bool timeless_decoding = true;
  508. u64 config;
  509. if (!pt->tsc_bit || !pt->cap_user_time_zero)
  510. return true;
  511. evlist__for_each(pt->session->evlist, evsel) {
  512. if (!(evsel->attr.sample_type & PERF_SAMPLE_TIME))
  513. return true;
  514. if (intel_pt_get_config(pt, &evsel->attr, &config)) {
  515. if (config & pt->tsc_bit)
  516. timeless_decoding = false;
  517. else
  518. return true;
  519. }
  520. }
  521. return timeless_decoding;
  522. }
  523. static bool intel_pt_tracing_kernel(struct intel_pt *pt)
  524. {
  525. struct perf_evsel *evsel;
  526. evlist__for_each(pt->session->evlist, evsel) {
  527. if (intel_pt_get_config(pt, &evsel->attr, NULL) &&
  528. !evsel->attr.exclude_kernel)
  529. return true;
  530. }
  531. return false;
  532. }
  533. static bool intel_pt_have_tsc(struct intel_pt *pt)
  534. {
  535. struct perf_evsel *evsel;
  536. bool have_tsc = false;
  537. u64 config;
  538. if (!pt->tsc_bit)
  539. return false;
  540. evlist__for_each(pt->session->evlist, evsel) {
  541. if (intel_pt_get_config(pt, &evsel->attr, &config)) {
  542. if (config & pt->tsc_bit)
  543. have_tsc = true;
  544. else
  545. return false;
  546. }
  547. }
  548. return have_tsc;
  549. }
  550. static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns)
  551. {
  552. u64 quot, rem;
  553. quot = ns / pt->tc.time_mult;
  554. rem = ns % pt->tc.time_mult;
  555. return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) /
  556. pt->tc.time_mult;
  557. }
  558. static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt,
  559. unsigned int queue_nr)
  560. {
  561. struct intel_pt_params params = { .get_trace = 0, };
  562. struct perf_env *env = pt->machine->env;
  563. struct intel_pt_queue *ptq;
  564. ptq = zalloc(sizeof(struct intel_pt_queue));
  565. if (!ptq)
  566. return NULL;
  567. if (pt->synth_opts.callchain) {
  568. size_t sz = sizeof(struct ip_callchain);
  569. sz += pt->synth_opts.callchain_sz * sizeof(u64);
  570. ptq->chain = zalloc(sz);
  571. if (!ptq->chain)
  572. goto out_free;
  573. }
  574. if (pt->synth_opts.last_branch) {
  575. size_t sz = sizeof(struct branch_stack);
  576. sz += pt->synth_opts.last_branch_sz *
  577. sizeof(struct branch_entry);
  578. ptq->last_branch = zalloc(sz);
  579. if (!ptq->last_branch)
  580. goto out_free;
  581. ptq->last_branch_rb = zalloc(sz);
  582. if (!ptq->last_branch_rb)
  583. goto out_free;
  584. }
  585. ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE);
  586. if (!ptq->event_buf)
  587. goto out_free;
  588. ptq->pt = pt;
  589. ptq->queue_nr = queue_nr;
  590. ptq->exclude_kernel = intel_pt_exclude_kernel(pt);
  591. ptq->pid = -1;
  592. ptq->tid = -1;
  593. ptq->cpu = -1;
  594. ptq->next_tid = -1;
  595. params.get_trace = intel_pt_get_trace;
  596. params.walk_insn = intel_pt_walk_next_insn;
  597. params.data = ptq;
  598. params.return_compression = intel_pt_return_compression(pt);
  599. params.max_non_turbo_ratio = pt->max_non_turbo_ratio;
  600. params.mtc_period = intel_pt_mtc_period(pt);
  601. params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n;
  602. params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d;
  603. if (pt->synth_opts.instructions) {
  604. if (pt->synth_opts.period) {
  605. switch (pt->synth_opts.period_type) {
  606. case PERF_ITRACE_PERIOD_INSTRUCTIONS:
  607. params.period_type =
  608. INTEL_PT_PERIOD_INSTRUCTIONS;
  609. params.period = pt->synth_opts.period;
  610. break;
  611. case PERF_ITRACE_PERIOD_TICKS:
  612. params.period_type = INTEL_PT_PERIOD_TICKS;
  613. params.period = pt->synth_opts.period;
  614. break;
  615. case PERF_ITRACE_PERIOD_NANOSECS:
  616. params.period_type = INTEL_PT_PERIOD_TICKS;
  617. params.period = intel_pt_ns_to_ticks(pt,
  618. pt->synth_opts.period);
  619. break;
  620. default:
  621. break;
  622. }
  623. }
  624. if (!params.period) {
  625. params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS;
  626. params.period = 1;
  627. }
  628. }
  629. if (env->cpuid && !strncmp(env->cpuid, "GenuineIntel,6,92,", 18))
  630. params.flags |= INTEL_PT_FUP_WITH_NLIP;
  631. ptq->decoder = intel_pt_decoder_new(&params);
  632. if (!ptq->decoder)
  633. goto out_free;
  634. return ptq;
  635. out_free:
  636. zfree(&ptq->event_buf);
  637. zfree(&ptq->last_branch);
  638. zfree(&ptq->last_branch_rb);
  639. zfree(&ptq->chain);
  640. free(ptq);
  641. return NULL;
  642. }
  643. static void intel_pt_free_queue(void *priv)
  644. {
  645. struct intel_pt_queue *ptq = priv;
  646. if (!ptq)
  647. return;
  648. thread__zput(ptq->thread);
  649. intel_pt_decoder_free(ptq->decoder);
  650. zfree(&ptq->event_buf);
  651. zfree(&ptq->last_branch);
  652. zfree(&ptq->last_branch_rb);
  653. zfree(&ptq->chain);
  654. free(ptq);
  655. }
  656. static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt,
  657. struct auxtrace_queue *queue)
  658. {
  659. struct intel_pt_queue *ptq = queue->priv;
  660. if (queue->tid == -1 || pt->have_sched_switch) {
  661. ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu);
  662. thread__zput(ptq->thread);
  663. }
  664. if (!ptq->thread && ptq->tid != -1)
  665. ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid);
  666. if (ptq->thread) {
  667. ptq->pid = ptq->thread->pid_;
  668. if (queue->cpu == -1)
  669. ptq->cpu = ptq->thread->cpu;
  670. }
  671. }
  672. static void intel_pt_sample_flags(struct intel_pt_queue *ptq)
  673. {
  674. if (ptq->state->flags & INTEL_PT_ABORT_TX) {
  675. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT;
  676. } else if (ptq->state->flags & INTEL_PT_ASYNC) {
  677. if (ptq->state->to_ip)
  678. ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL |
  679. PERF_IP_FLAG_ASYNC |
  680. PERF_IP_FLAG_INTERRUPT;
  681. else
  682. ptq->flags = PERF_IP_FLAG_BRANCH |
  683. PERF_IP_FLAG_TRACE_END;
  684. ptq->insn_len = 0;
  685. } else {
  686. if (ptq->state->from_ip)
  687. ptq->flags = intel_pt_insn_type(ptq->state->insn_op);
  688. else
  689. ptq->flags = PERF_IP_FLAG_BRANCH |
  690. PERF_IP_FLAG_TRACE_BEGIN;
  691. if (ptq->state->flags & INTEL_PT_IN_TX)
  692. ptq->flags |= PERF_IP_FLAG_IN_TX;
  693. ptq->insn_len = ptq->state->insn_len;
  694. }
  695. }
  696. static int intel_pt_setup_queue(struct intel_pt *pt,
  697. struct auxtrace_queue *queue,
  698. unsigned int queue_nr)
  699. {
  700. struct intel_pt_queue *ptq = queue->priv;
  701. if (list_empty(&queue->head))
  702. return 0;
  703. if (!ptq) {
  704. ptq = intel_pt_alloc_queue(pt, queue_nr);
  705. if (!ptq)
  706. return -ENOMEM;
  707. queue->priv = ptq;
  708. if (queue->cpu != -1)
  709. ptq->cpu = queue->cpu;
  710. ptq->tid = queue->tid;
  711. if (pt->sampling_mode) {
  712. if (pt->timeless_decoding)
  713. ptq->step_through_buffers = true;
  714. if (pt->timeless_decoding || !pt->have_sched_switch)
  715. ptq->use_buffer_pid_tid = true;
  716. }
  717. ptq->sync_switch = pt->sync_switch;
  718. }
  719. if (!ptq->on_heap &&
  720. (!ptq->sync_switch ||
  721. ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) {
  722. const struct intel_pt_state *state;
  723. int ret;
  724. if (pt->timeless_decoding)
  725. return 0;
  726. intel_pt_log("queue %u getting timestamp\n", queue_nr);
  727. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  728. queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  729. while (1) {
  730. state = intel_pt_decode(ptq->decoder);
  731. if (state->err) {
  732. if (state->err == INTEL_PT_ERR_NODATA) {
  733. intel_pt_log("queue %u has no timestamp\n",
  734. queue_nr);
  735. return 0;
  736. }
  737. continue;
  738. }
  739. if (state->timestamp)
  740. break;
  741. }
  742. ptq->timestamp = state->timestamp;
  743. intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n",
  744. queue_nr, ptq->timestamp);
  745. ptq->state = state;
  746. ptq->have_sample = true;
  747. intel_pt_sample_flags(ptq);
  748. ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp);
  749. if (ret)
  750. return ret;
  751. ptq->on_heap = true;
  752. }
  753. return 0;
  754. }
  755. static int intel_pt_setup_queues(struct intel_pt *pt)
  756. {
  757. unsigned int i;
  758. int ret;
  759. for (i = 0; i < pt->queues.nr_queues; i++) {
  760. ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i);
  761. if (ret)
  762. return ret;
  763. }
  764. return 0;
  765. }
  766. static inline void intel_pt_copy_last_branch_rb(struct intel_pt_queue *ptq)
  767. {
  768. struct branch_stack *bs_src = ptq->last_branch_rb;
  769. struct branch_stack *bs_dst = ptq->last_branch;
  770. size_t nr = 0;
  771. bs_dst->nr = bs_src->nr;
  772. if (!bs_src->nr)
  773. return;
  774. nr = ptq->pt->synth_opts.last_branch_sz - ptq->last_branch_pos;
  775. memcpy(&bs_dst->entries[0],
  776. &bs_src->entries[ptq->last_branch_pos],
  777. sizeof(struct branch_entry) * nr);
  778. if (bs_src->nr >= ptq->pt->synth_opts.last_branch_sz) {
  779. memcpy(&bs_dst->entries[nr],
  780. &bs_src->entries[0],
  781. sizeof(struct branch_entry) * ptq->last_branch_pos);
  782. }
  783. }
  784. static inline void intel_pt_reset_last_branch_rb(struct intel_pt_queue *ptq)
  785. {
  786. ptq->last_branch_pos = 0;
  787. ptq->last_branch_rb->nr = 0;
  788. }
  789. static void intel_pt_update_last_branch_rb(struct intel_pt_queue *ptq)
  790. {
  791. const struct intel_pt_state *state = ptq->state;
  792. struct branch_stack *bs = ptq->last_branch_rb;
  793. struct branch_entry *be;
  794. if (!ptq->last_branch_pos)
  795. ptq->last_branch_pos = ptq->pt->synth_opts.last_branch_sz;
  796. ptq->last_branch_pos -= 1;
  797. be = &bs->entries[ptq->last_branch_pos];
  798. be->from = state->from_ip;
  799. be->to = state->to_ip;
  800. be->flags.abort = !!(state->flags & INTEL_PT_ABORT_TX);
  801. be->flags.in_tx = !!(state->flags & INTEL_PT_IN_TX);
  802. /* No support for mispredict */
  803. be->flags.mispred = ptq->pt->mispred_all;
  804. if (bs->nr < ptq->pt->synth_opts.last_branch_sz)
  805. bs->nr += 1;
  806. }
  807. static int intel_pt_inject_event(union perf_event *event,
  808. struct perf_sample *sample, u64 type,
  809. bool swapped)
  810. {
  811. event->header.size = perf_event__sample_event_size(sample, type, 0);
  812. return perf_event__synthesize_sample(event, type, 0, sample, swapped);
  813. }
  814. static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq)
  815. {
  816. int ret;
  817. struct intel_pt *pt = ptq->pt;
  818. union perf_event *event = ptq->event_buf;
  819. struct perf_sample sample = { .ip = 0, };
  820. struct dummy_branch_stack {
  821. u64 nr;
  822. struct branch_entry entries;
  823. } dummy_bs;
  824. if (pt->branches_filter && !(pt->branches_filter & ptq->flags))
  825. return 0;
  826. event->sample.header.type = PERF_RECORD_SAMPLE;
  827. event->sample.header.misc = PERF_RECORD_MISC_USER;
  828. event->sample.header.size = sizeof(struct perf_event_header);
  829. if (!pt->timeless_decoding)
  830. sample.time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
  831. sample.ip = ptq->state->from_ip;
  832. sample.pid = ptq->pid;
  833. sample.tid = ptq->tid;
  834. sample.addr = ptq->state->to_ip;
  835. sample.id = ptq->pt->branches_id;
  836. sample.stream_id = ptq->pt->branches_id;
  837. sample.period = 1;
  838. sample.cpu = ptq->cpu;
  839. sample.flags = ptq->flags;
  840. sample.insn_len = ptq->insn_len;
  841. /*
  842. * perf report cannot handle events without a branch stack when using
  843. * SORT_MODE__BRANCH so make a dummy one.
  844. */
  845. if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) {
  846. dummy_bs = (struct dummy_branch_stack){
  847. .nr = 1,
  848. .entries = {
  849. .from = sample.ip,
  850. .to = sample.addr,
  851. },
  852. };
  853. sample.branch_stack = (struct branch_stack *)&dummy_bs;
  854. }
  855. if (pt->synth_opts.inject) {
  856. ret = intel_pt_inject_event(event, &sample,
  857. pt->branches_sample_type,
  858. pt->synth_needs_swap);
  859. if (ret)
  860. return ret;
  861. }
  862. ret = perf_session__deliver_synth_event(pt->session, event, &sample);
  863. if (ret)
  864. pr_err("Intel Processor Trace: failed to deliver branch event, error %d\n",
  865. ret);
  866. return ret;
  867. }
  868. static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq)
  869. {
  870. int ret;
  871. struct intel_pt *pt = ptq->pt;
  872. union perf_event *event = ptq->event_buf;
  873. struct perf_sample sample = { .ip = 0, };
  874. event->sample.header.type = PERF_RECORD_SAMPLE;
  875. event->sample.header.misc = PERF_RECORD_MISC_USER;
  876. event->sample.header.size = sizeof(struct perf_event_header);
  877. if (!pt->timeless_decoding)
  878. sample.time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
  879. sample.ip = ptq->state->from_ip;
  880. sample.pid = ptq->pid;
  881. sample.tid = ptq->tid;
  882. sample.addr = ptq->state->to_ip;
  883. sample.id = ptq->pt->instructions_id;
  884. sample.stream_id = ptq->pt->instructions_id;
  885. sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt;
  886. sample.cpu = ptq->cpu;
  887. sample.flags = ptq->flags;
  888. sample.insn_len = ptq->insn_len;
  889. ptq->last_insn_cnt = ptq->state->tot_insn_cnt;
  890. if (pt->synth_opts.callchain) {
  891. thread_stack__sample(ptq->thread, ptq->chain,
  892. pt->synth_opts.callchain_sz, sample.ip);
  893. sample.callchain = ptq->chain;
  894. }
  895. if (pt->synth_opts.last_branch) {
  896. intel_pt_copy_last_branch_rb(ptq);
  897. sample.branch_stack = ptq->last_branch;
  898. }
  899. if (pt->synth_opts.inject) {
  900. ret = intel_pt_inject_event(event, &sample,
  901. pt->instructions_sample_type,
  902. pt->synth_needs_swap);
  903. if (ret)
  904. return ret;
  905. }
  906. ret = perf_session__deliver_synth_event(pt->session, event, &sample);
  907. if (ret)
  908. pr_err("Intel Processor Trace: failed to deliver instruction event, error %d\n",
  909. ret);
  910. if (pt->synth_opts.last_branch)
  911. intel_pt_reset_last_branch_rb(ptq);
  912. return ret;
  913. }
  914. static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq)
  915. {
  916. int ret;
  917. struct intel_pt *pt = ptq->pt;
  918. union perf_event *event = ptq->event_buf;
  919. struct perf_sample sample = { .ip = 0, };
  920. event->sample.header.type = PERF_RECORD_SAMPLE;
  921. event->sample.header.misc = PERF_RECORD_MISC_USER;
  922. event->sample.header.size = sizeof(struct perf_event_header);
  923. if (!pt->timeless_decoding)
  924. sample.time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
  925. sample.ip = ptq->state->from_ip;
  926. sample.pid = ptq->pid;
  927. sample.tid = ptq->tid;
  928. sample.addr = ptq->state->to_ip;
  929. sample.id = ptq->pt->transactions_id;
  930. sample.stream_id = ptq->pt->transactions_id;
  931. sample.period = 1;
  932. sample.cpu = ptq->cpu;
  933. sample.flags = ptq->flags;
  934. sample.insn_len = ptq->insn_len;
  935. if (pt->synth_opts.callchain) {
  936. thread_stack__sample(ptq->thread, ptq->chain,
  937. pt->synth_opts.callchain_sz, sample.ip);
  938. sample.callchain = ptq->chain;
  939. }
  940. if (pt->synth_opts.last_branch) {
  941. intel_pt_copy_last_branch_rb(ptq);
  942. sample.branch_stack = ptq->last_branch;
  943. }
  944. if (pt->synth_opts.inject) {
  945. ret = intel_pt_inject_event(event, &sample,
  946. pt->transactions_sample_type,
  947. pt->synth_needs_swap);
  948. if (ret)
  949. return ret;
  950. }
  951. ret = perf_session__deliver_synth_event(pt->session, event, &sample);
  952. if (ret)
  953. pr_err("Intel Processor Trace: failed to deliver transaction event, error %d\n",
  954. ret);
  955. if (pt->synth_opts.last_branch)
  956. intel_pt_reset_last_branch_rb(ptq);
  957. return ret;
  958. }
  959. static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu,
  960. pid_t pid, pid_t tid, u64 ip)
  961. {
  962. union perf_event event;
  963. char msg[MAX_AUXTRACE_ERROR_MSG];
  964. int err;
  965. intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG);
  966. auxtrace_synth_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE,
  967. code, cpu, pid, tid, ip, msg);
  968. err = perf_session__deliver_synth_event(pt->session, &event, NULL);
  969. if (err)
  970. pr_err("Intel Processor Trace: failed to deliver error event, error %d\n",
  971. err);
  972. return err;
  973. }
  974. static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq)
  975. {
  976. struct auxtrace_queue *queue;
  977. pid_t tid = ptq->next_tid;
  978. int err;
  979. if (tid == -1)
  980. return 0;
  981. intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid);
  982. err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid);
  983. queue = &pt->queues.queue_array[ptq->queue_nr];
  984. intel_pt_set_pid_tid_cpu(pt, queue);
  985. ptq->next_tid = -1;
  986. return err;
  987. }
  988. static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip)
  989. {
  990. struct intel_pt *pt = ptq->pt;
  991. return ip == pt->switch_ip &&
  992. (ptq->flags & PERF_IP_FLAG_BRANCH) &&
  993. !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC |
  994. PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT));
  995. }
  996. static int intel_pt_sample(struct intel_pt_queue *ptq)
  997. {
  998. const struct intel_pt_state *state = ptq->state;
  999. struct intel_pt *pt = ptq->pt;
  1000. int err;
  1001. if (!ptq->have_sample)
  1002. return 0;
  1003. ptq->have_sample = false;
  1004. if (pt->sample_instructions &&
  1005. (state->type & INTEL_PT_INSTRUCTION)) {
  1006. err = intel_pt_synth_instruction_sample(ptq);
  1007. if (err)
  1008. return err;
  1009. }
  1010. if (pt->sample_transactions &&
  1011. (state->type & INTEL_PT_TRANSACTION)) {
  1012. err = intel_pt_synth_transaction_sample(ptq);
  1013. if (err)
  1014. return err;
  1015. }
  1016. if (!(state->type & INTEL_PT_BRANCH))
  1017. return 0;
  1018. if (pt->synth_opts.callchain)
  1019. thread_stack__event(ptq->thread, ptq->flags, state->from_ip,
  1020. state->to_ip, ptq->insn_len,
  1021. state->trace_nr);
  1022. else
  1023. thread_stack__set_trace_nr(ptq->thread, state->trace_nr);
  1024. if (pt->sample_branches) {
  1025. err = intel_pt_synth_branch_sample(ptq);
  1026. if (err)
  1027. return err;
  1028. }
  1029. if (pt->synth_opts.last_branch)
  1030. intel_pt_update_last_branch_rb(ptq);
  1031. if (!ptq->sync_switch)
  1032. return 0;
  1033. if (intel_pt_is_switch_ip(ptq, state->to_ip)) {
  1034. switch (ptq->switch_state) {
  1035. case INTEL_PT_SS_NOT_TRACING:
  1036. case INTEL_PT_SS_UNKNOWN:
  1037. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1038. err = intel_pt_next_tid(pt, ptq);
  1039. if (err)
  1040. return err;
  1041. ptq->switch_state = INTEL_PT_SS_TRACING;
  1042. break;
  1043. default:
  1044. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT;
  1045. return 1;
  1046. }
  1047. } else if (!state->to_ip) {
  1048. ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
  1049. } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) {
  1050. ptq->switch_state = INTEL_PT_SS_UNKNOWN;
  1051. } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1052. state->to_ip == pt->ptss_ip &&
  1053. (ptq->flags & PERF_IP_FLAG_CALL)) {
  1054. ptq->switch_state = INTEL_PT_SS_TRACING;
  1055. }
  1056. return 0;
  1057. }
  1058. static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip)
  1059. {
  1060. struct machine *machine = pt->machine;
  1061. struct map *map;
  1062. struct symbol *sym, *start;
  1063. u64 ip, switch_ip = 0;
  1064. const char *ptss;
  1065. if (ptss_ip)
  1066. *ptss_ip = 0;
  1067. map = machine__kernel_map(machine);
  1068. if (!map)
  1069. return 0;
  1070. if (map__load(map, machine->symbol_filter))
  1071. return 0;
  1072. start = dso__first_symbol(map->dso, MAP__FUNCTION);
  1073. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1074. if (sym->binding == STB_GLOBAL &&
  1075. !strcmp(sym->name, "__switch_to")) {
  1076. ip = map->unmap_ip(map, sym->start);
  1077. if (ip >= map->start && ip < map->end) {
  1078. switch_ip = ip;
  1079. break;
  1080. }
  1081. }
  1082. }
  1083. if (!switch_ip || !ptss_ip)
  1084. return 0;
  1085. if (pt->have_sched_switch == 1)
  1086. ptss = "perf_trace_sched_switch";
  1087. else
  1088. ptss = "__perf_event_task_sched_out";
  1089. for (sym = start; sym; sym = dso__next_symbol(sym)) {
  1090. if (!strcmp(sym->name, ptss)) {
  1091. ip = map->unmap_ip(map, sym->start);
  1092. if (ip >= map->start && ip < map->end) {
  1093. *ptss_ip = ip;
  1094. break;
  1095. }
  1096. }
  1097. }
  1098. return switch_ip;
  1099. }
  1100. static void intel_pt_enable_sync_switch(struct intel_pt *pt)
  1101. {
  1102. unsigned int i;
  1103. pt->sync_switch = true;
  1104. for (i = 0; i < pt->queues.nr_queues; i++) {
  1105. struct auxtrace_queue *queue = &pt->queues.queue_array[i];
  1106. struct intel_pt_queue *ptq = queue->priv;
  1107. if (ptq)
  1108. ptq->sync_switch = true;
  1109. }
  1110. }
  1111. static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp)
  1112. {
  1113. const struct intel_pt_state *state = ptq->state;
  1114. struct intel_pt *pt = ptq->pt;
  1115. int err;
  1116. if (!pt->kernel_start) {
  1117. pt->kernel_start = machine__kernel_start(pt->machine);
  1118. if (pt->per_cpu_mmaps &&
  1119. (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) &&
  1120. !pt->timeless_decoding && intel_pt_tracing_kernel(pt) &&
  1121. !pt->sampling_mode) {
  1122. pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip);
  1123. if (pt->switch_ip) {
  1124. intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n",
  1125. pt->switch_ip, pt->ptss_ip);
  1126. intel_pt_enable_sync_switch(pt);
  1127. }
  1128. }
  1129. }
  1130. intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
  1131. ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
  1132. while (1) {
  1133. err = intel_pt_sample(ptq);
  1134. if (err)
  1135. return err;
  1136. state = intel_pt_decode(ptq->decoder);
  1137. if (state->err) {
  1138. if (state->err == INTEL_PT_ERR_NODATA)
  1139. return 1;
  1140. if (ptq->sync_switch &&
  1141. state->from_ip >= pt->kernel_start) {
  1142. ptq->sync_switch = false;
  1143. intel_pt_next_tid(pt, ptq);
  1144. }
  1145. if (pt->synth_opts.errors) {
  1146. err = intel_pt_synth_error(pt, state->err,
  1147. ptq->cpu, ptq->pid,
  1148. ptq->tid,
  1149. state->from_ip);
  1150. if (err)
  1151. return err;
  1152. }
  1153. continue;
  1154. }
  1155. ptq->state = state;
  1156. ptq->have_sample = true;
  1157. intel_pt_sample_flags(ptq);
  1158. /* Use estimated TSC upon return to user space */
  1159. if (pt->est_tsc &&
  1160. (state->from_ip >= pt->kernel_start || !state->from_ip) &&
  1161. state->to_ip && state->to_ip < pt->kernel_start) {
  1162. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1163. state->timestamp, state->est_timestamp);
  1164. ptq->timestamp = state->est_timestamp;
  1165. /* Use estimated TSC in unknown switch state */
  1166. } else if (ptq->sync_switch &&
  1167. ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
  1168. intel_pt_is_switch_ip(ptq, state->to_ip) &&
  1169. ptq->next_tid == -1) {
  1170. intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
  1171. state->timestamp, state->est_timestamp);
  1172. ptq->timestamp = state->est_timestamp;
  1173. } else if (state->timestamp > ptq->timestamp) {
  1174. ptq->timestamp = state->timestamp;
  1175. }
  1176. if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) {
  1177. *timestamp = ptq->timestamp;
  1178. return 0;
  1179. }
  1180. }
  1181. return 0;
  1182. }
  1183. static inline int intel_pt_update_queues(struct intel_pt *pt)
  1184. {
  1185. if (pt->queues.new_data) {
  1186. pt->queues.new_data = false;
  1187. return intel_pt_setup_queues(pt);
  1188. }
  1189. return 0;
  1190. }
  1191. static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp)
  1192. {
  1193. unsigned int queue_nr;
  1194. u64 ts;
  1195. int ret;
  1196. while (1) {
  1197. struct auxtrace_queue *queue;
  1198. struct intel_pt_queue *ptq;
  1199. if (!pt->heap.heap_cnt)
  1200. return 0;
  1201. if (pt->heap.heap_array[0].ordinal >= timestamp)
  1202. return 0;
  1203. queue_nr = pt->heap.heap_array[0].queue_nr;
  1204. queue = &pt->queues.queue_array[queue_nr];
  1205. ptq = queue->priv;
  1206. intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n",
  1207. queue_nr, pt->heap.heap_array[0].ordinal,
  1208. timestamp);
  1209. auxtrace_heap__pop(&pt->heap);
  1210. if (pt->heap.heap_cnt) {
  1211. ts = pt->heap.heap_array[0].ordinal + 1;
  1212. if (ts > timestamp)
  1213. ts = timestamp;
  1214. } else {
  1215. ts = timestamp;
  1216. }
  1217. intel_pt_set_pid_tid_cpu(pt, queue);
  1218. ret = intel_pt_run_decoder(ptq, &ts);
  1219. if (ret < 0) {
  1220. auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1221. return ret;
  1222. }
  1223. if (!ret) {
  1224. ret = auxtrace_heap__add(&pt->heap, queue_nr, ts);
  1225. if (ret < 0)
  1226. return ret;
  1227. } else {
  1228. ptq->on_heap = false;
  1229. }
  1230. }
  1231. return 0;
  1232. }
  1233. static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid,
  1234. u64 time_)
  1235. {
  1236. struct auxtrace_queues *queues = &pt->queues;
  1237. unsigned int i;
  1238. u64 ts = 0;
  1239. for (i = 0; i < queues->nr_queues; i++) {
  1240. struct auxtrace_queue *queue = &pt->queues.queue_array[i];
  1241. struct intel_pt_queue *ptq = queue->priv;
  1242. if (ptq && (tid == -1 || ptq->tid == tid)) {
  1243. ptq->time = time_;
  1244. intel_pt_set_pid_tid_cpu(pt, queue);
  1245. intel_pt_run_decoder(ptq, &ts);
  1246. }
  1247. }
  1248. return 0;
  1249. }
  1250. static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample)
  1251. {
  1252. return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu,
  1253. sample->pid, sample->tid, 0);
  1254. }
  1255. static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu)
  1256. {
  1257. unsigned i, j;
  1258. if (cpu < 0 || !pt->queues.nr_queues)
  1259. return NULL;
  1260. if ((unsigned)cpu >= pt->queues.nr_queues)
  1261. i = pt->queues.nr_queues - 1;
  1262. else
  1263. i = cpu;
  1264. if (pt->queues.queue_array[i].cpu == cpu)
  1265. return pt->queues.queue_array[i].priv;
  1266. for (j = 0; i > 0; j++) {
  1267. if (pt->queues.queue_array[--i].cpu == cpu)
  1268. return pt->queues.queue_array[i].priv;
  1269. }
  1270. for (; j < pt->queues.nr_queues; j++) {
  1271. if (pt->queues.queue_array[j].cpu == cpu)
  1272. return pt->queues.queue_array[j].priv;
  1273. }
  1274. return NULL;
  1275. }
  1276. static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid,
  1277. u64 timestamp)
  1278. {
  1279. struct intel_pt_queue *ptq;
  1280. int err;
  1281. if (!pt->sync_switch)
  1282. return 1;
  1283. ptq = intel_pt_cpu_to_ptq(pt, cpu);
  1284. if (!ptq || !ptq->sync_switch)
  1285. return 1;
  1286. switch (ptq->switch_state) {
  1287. case INTEL_PT_SS_NOT_TRACING:
  1288. ptq->next_tid = -1;
  1289. break;
  1290. case INTEL_PT_SS_UNKNOWN:
  1291. case INTEL_PT_SS_TRACING:
  1292. ptq->next_tid = tid;
  1293. ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP;
  1294. return 0;
  1295. case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
  1296. if (!ptq->on_heap) {
  1297. ptq->timestamp = perf_time_to_tsc(timestamp,
  1298. &pt->tc);
  1299. err = auxtrace_heap__add(&pt->heap, ptq->queue_nr,
  1300. ptq->timestamp);
  1301. if (err)
  1302. return err;
  1303. ptq->on_heap = true;
  1304. }
  1305. ptq->switch_state = INTEL_PT_SS_TRACING;
  1306. break;
  1307. case INTEL_PT_SS_EXPECTING_SWITCH_IP:
  1308. ptq->next_tid = tid;
  1309. intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu);
  1310. break;
  1311. default:
  1312. break;
  1313. }
  1314. return 1;
  1315. }
  1316. static int intel_pt_process_switch(struct intel_pt *pt,
  1317. struct perf_sample *sample)
  1318. {
  1319. struct perf_evsel *evsel;
  1320. pid_t tid;
  1321. int cpu, ret;
  1322. evsel = perf_evlist__id2evsel(pt->session->evlist, sample->id);
  1323. if (evsel != pt->switch_evsel)
  1324. return 0;
  1325. tid = perf_evsel__intval(evsel, sample, "next_pid");
  1326. cpu = sample->cpu;
  1327. intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1328. cpu, tid, sample->time, perf_time_to_tsc(sample->time,
  1329. &pt->tc));
  1330. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  1331. if (ret <= 0)
  1332. return ret;
  1333. return machine__set_current_tid(pt->machine, cpu, -1, tid);
  1334. }
  1335. static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event,
  1336. struct perf_sample *sample)
  1337. {
  1338. bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT;
  1339. pid_t pid, tid;
  1340. int cpu, ret;
  1341. cpu = sample->cpu;
  1342. if (pt->have_sched_switch == 3) {
  1343. if (!out)
  1344. return 0;
  1345. if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) {
  1346. pr_err("Expecting CPU-wide context switch event\n");
  1347. return -EINVAL;
  1348. }
  1349. pid = event->context_switch.next_prev_pid;
  1350. tid = event->context_switch.next_prev_tid;
  1351. } else {
  1352. if (out)
  1353. return 0;
  1354. pid = sample->pid;
  1355. tid = sample->tid;
  1356. }
  1357. if (tid == -1) {
  1358. pr_err("context_switch event has no tid\n");
  1359. return -EINVAL;
  1360. }
  1361. intel_pt_log("context_switch: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1362. cpu, pid, tid, sample->time, perf_time_to_tsc(sample->time,
  1363. &pt->tc));
  1364. ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
  1365. if (ret <= 0)
  1366. return ret;
  1367. return machine__set_current_tid(pt->machine, cpu, pid, tid);
  1368. }
  1369. static int intel_pt_process_itrace_start(struct intel_pt *pt,
  1370. union perf_event *event,
  1371. struct perf_sample *sample)
  1372. {
  1373. if (!pt->per_cpu_mmaps)
  1374. return 0;
  1375. intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
  1376. sample->cpu, event->itrace_start.pid,
  1377. event->itrace_start.tid, sample->time,
  1378. perf_time_to_tsc(sample->time, &pt->tc));
  1379. return machine__set_current_tid(pt->machine, sample->cpu,
  1380. event->itrace_start.pid,
  1381. event->itrace_start.tid);
  1382. }
  1383. static int intel_pt_process_event(struct perf_session *session,
  1384. union perf_event *event,
  1385. struct perf_sample *sample,
  1386. struct perf_tool *tool)
  1387. {
  1388. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1389. auxtrace);
  1390. u64 timestamp;
  1391. int err = 0;
  1392. if (dump_trace)
  1393. return 0;
  1394. if (!tool->ordered_events) {
  1395. pr_err("Intel Processor Trace requires ordered events\n");
  1396. return -EINVAL;
  1397. }
  1398. if (sample->time && sample->time != (u64)-1)
  1399. timestamp = perf_time_to_tsc(sample->time, &pt->tc);
  1400. else
  1401. timestamp = 0;
  1402. if (timestamp || pt->timeless_decoding) {
  1403. err = intel_pt_update_queues(pt);
  1404. if (err)
  1405. return err;
  1406. }
  1407. if (pt->timeless_decoding) {
  1408. if (event->header.type == PERF_RECORD_EXIT) {
  1409. err = intel_pt_process_timeless_queues(pt,
  1410. event->fork.tid,
  1411. sample->time);
  1412. }
  1413. } else if (timestamp) {
  1414. err = intel_pt_process_queues(pt, timestamp);
  1415. }
  1416. if (err)
  1417. return err;
  1418. if (event->header.type == PERF_RECORD_AUX &&
  1419. (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) &&
  1420. pt->synth_opts.errors) {
  1421. err = intel_pt_lost(pt, sample);
  1422. if (err)
  1423. return err;
  1424. }
  1425. if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE)
  1426. err = intel_pt_process_switch(pt, sample);
  1427. else if (event->header.type == PERF_RECORD_ITRACE_START)
  1428. err = intel_pt_process_itrace_start(pt, event, sample);
  1429. else if (event->header.type == PERF_RECORD_SWITCH ||
  1430. event->header.type == PERF_RECORD_SWITCH_CPU_WIDE)
  1431. err = intel_pt_context_switch(pt, event, sample);
  1432. intel_pt_log("event %s (%u): cpu %d time %"PRIu64" tsc %#"PRIx64"\n",
  1433. perf_event__name(event->header.type), event->header.type,
  1434. sample->cpu, sample->time, timestamp);
  1435. return err;
  1436. }
  1437. static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool)
  1438. {
  1439. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1440. auxtrace);
  1441. int ret;
  1442. if (dump_trace)
  1443. return 0;
  1444. if (!tool->ordered_events)
  1445. return -EINVAL;
  1446. ret = intel_pt_update_queues(pt);
  1447. if (ret < 0)
  1448. return ret;
  1449. if (pt->timeless_decoding)
  1450. return intel_pt_process_timeless_queues(pt, -1,
  1451. MAX_TIMESTAMP - 1);
  1452. return intel_pt_process_queues(pt, MAX_TIMESTAMP);
  1453. }
  1454. static void intel_pt_free_events(struct perf_session *session)
  1455. {
  1456. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1457. auxtrace);
  1458. struct auxtrace_queues *queues = &pt->queues;
  1459. unsigned int i;
  1460. for (i = 0; i < queues->nr_queues; i++) {
  1461. intel_pt_free_queue(queues->queue_array[i].priv);
  1462. queues->queue_array[i].priv = NULL;
  1463. }
  1464. intel_pt_log_disable();
  1465. auxtrace_queues__free(queues);
  1466. }
  1467. static void intel_pt_free(struct perf_session *session)
  1468. {
  1469. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1470. auxtrace);
  1471. auxtrace_heap__free(&pt->heap);
  1472. intel_pt_free_events(session);
  1473. session->auxtrace = NULL;
  1474. thread__delete(pt->unknown_thread);
  1475. free(pt);
  1476. }
  1477. static int intel_pt_process_auxtrace_event(struct perf_session *session,
  1478. union perf_event *event,
  1479. struct perf_tool *tool __maybe_unused)
  1480. {
  1481. struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
  1482. auxtrace);
  1483. if (pt->sampling_mode)
  1484. return 0;
  1485. if (!pt->data_queued) {
  1486. struct auxtrace_buffer *buffer;
  1487. off_t data_offset;
  1488. int fd = perf_data_file__fd(session->file);
  1489. int err;
  1490. if (perf_data_file__is_pipe(session->file)) {
  1491. data_offset = 0;
  1492. } else {
  1493. data_offset = lseek(fd, 0, SEEK_CUR);
  1494. if (data_offset == -1)
  1495. return -errno;
  1496. }
  1497. err = auxtrace_queues__add_event(&pt->queues, session, event,
  1498. data_offset, &buffer);
  1499. if (err)
  1500. return err;
  1501. /* Dump here now we have copied a piped trace out of the pipe */
  1502. if (dump_trace) {
  1503. if (auxtrace_buffer__get_data(buffer, fd)) {
  1504. intel_pt_dump_event(pt, buffer->data,
  1505. buffer->size);
  1506. auxtrace_buffer__put_data(buffer);
  1507. }
  1508. }
  1509. }
  1510. return 0;
  1511. }
  1512. struct intel_pt_synth {
  1513. struct perf_tool dummy_tool;
  1514. struct perf_session *session;
  1515. };
  1516. static int intel_pt_event_synth(struct perf_tool *tool,
  1517. union perf_event *event,
  1518. struct perf_sample *sample __maybe_unused,
  1519. struct machine *machine __maybe_unused)
  1520. {
  1521. struct intel_pt_synth *intel_pt_synth =
  1522. container_of(tool, struct intel_pt_synth, dummy_tool);
  1523. return perf_session__deliver_synth_event(intel_pt_synth->session, event,
  1524. NULL);
  1525. }
  1526. static int intel_pt_synth_event(struct perf_session *session,
  1527. struct perf_event_attr *attr, u64 id)
  1528. {
  1529. struct intel_pt_synth intel_pt_synth;
  1530. memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth));
  1531. intel_pt_synth.session = session;
  1532. return perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1,
  1533. &id, intel_pt_event_synth);
  1534. }
  1535. static int intel_pt_synth_events(struct intel_pt *pt,
  1536. struct perf_session *session)
  1537. {
  1538. struct perf_evlist *evlist = session->evlist;
  1539. struct perf_evsel *evsel;
  1540. struct perf_event_attr attr;
  1541. bool found = false;
  1542. u64 id;
  1543. int err;
  1544. evlist__for_each(evlist, evsel) {
  1545. if (evsel->attr.type == pt->pmu_type && evsel->ids) {
  1546. found = true;
  1547. break;
  1548. }
  1549. }
  1550. if (!found) {
  1551. pr_debug("There are no selected events with Intel Processor Trace data\n");
  1552. return 0;
  1553. }
  1554. memset(&attr, 0, sizeof(struct perf_event_attr));
  1555. attr.size = sizeof(struct perf_event_attr);
  1556. attr.type = PERF_TYPE_HARDWARE;
  1557. attr.sample_type = evsel->attr.sample_type & PERF_SAMPLE_MASK;
  1558. attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID |
  1559. PERF_SAMPLE_PERIOD;
  1560. if (pt->timeless_decoding)
  1561. attr.sample_type &= ~(u64)PERF_SAMPLE_TIME;
  1562. else
  1563. attr.sample_type |= PERF_SAMPLE_TIME;
  1564. if (!pt->per_cpu_mmaps)
  1565. attr.sample_type &= ~(u64)PERF_SAMPLE_CPU;
  1566. attr.exclude_user = evsel->attr.exclude_user;
  1567. attr.exclude_kernel = evsel->attr.exclude_kernel;
  1568. attr.exclude_hv = evsel->attr.exclude_hv;
  1569. attr.exclude_host = evsel->attr.exclude_host;
  1570. attr.exclude_guest = evsel->attr.exclude_guest;
  1571. attr.sample_id_all = evsel->attr.sample_id_all;
  1572. attr.read_format = evsel->attr.read_format;
  1573. id = evsel->id[0] + 1000000000;
  1574. if (!id)
  1575. id = 1;
  1576. if (pt->synth_opts.instructions) {
  1577. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  1578. if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS)
  1579. attr.sample_period =
  1580. intel_pt_ns_to_ticks(pt, pt->synth_opts.period);
  1581. else
  1582. attr.sample_period = pt->synth_opts.period;
  1583. pt->instructions_sample_period = attr.sample_period;
  1584. if (pt->synth_opts.callchain)
  1585. attr.sample_type |= PERF_SAMPLE_CALLCHAIN;
  1586. if (pt->synth_opts.last_branch)
  1587. attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
  1588. pr_debug("Synthesizing 'instructions' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
  1589. id, (u64)attr.sample_type);
  1590. err = intel_pt_synth_event(session, &attr, id);
  1591. if (err) {
  1592. pr_err("%s: failed to synthesize 'instructions' event type\n",
  1593. __func__);
  1594. return err;
  1595. }
  1596. pt->sample_instructions = true;
  1597. pt->instructions_sample_type = attr.sample_type;
  1598. pt->instructions_id = id;
  1599. id += 1;
  1600. }
  1601. if (pt->synth_opts.transactions) {
  1602. attr.config = PERF_COUNT_HW_INSTRUCTIONS;
  1603. attr.sample_period = 1;
  1604. if (pt->synth_opts.callchain)
  1605. attr.sample_type |= PERF_SAMPLE_CALLCHAIN;
  1606. if (pt->synth_opts.last_branch)
  1607. attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
  1608. pr_debug("Synthesizing 'transactions' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
  1609. id, (u64)attr.sample_type);
  1610. err = intel_pt_synth_event(session, &attr, id);
  1611. if (err) {
  1612. pr_err("%s: failed to synthesize 'transactions' event type\n",
  1613. __func__);
  1614. return err;
  1615. }
  1616. pt->sample_transactions = true;
  1617. pt->transactions_id = id;
  1618. id += 1;
  1619. evlist__for_each(evlist, evsel) {
  1620. if (evsel->id && evsel->id[0] == pt->transactions_id) {
  1621. if (evsel->name)
  1622. zfree(&evsel->name);
  1623. evsel->name = strdup("transactions");
  1624. break;
  1625. }
  1626. }
  1627. }
  1628. if (pt->synth_opts.branches) {
  1629. attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
  1630. attr.sample_period = 1;
  1631. attr.sample_type |= PERF_SAMPLE_ADDR;
  1632. attr.sample_type &= ~(u64)PERF_SAMPLE_CALLCHAIN;
  1633. attr.sample_type &= ~(u64)PERF_SAMPLE_BRANCH_STACK;
  1634. pr_debug("Synthesizing 'branches' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
  1635. id, (u64)attr.sample_type);
  1636. err = intel_pt_synth_event(session, &attr, id);
  1637. if (err) {
  1638. pr_err("%s: failed to synthesize 'branches' event type\n",
  1639. __func__);
  1640. return err;
  1641. }
  1642. pt->sample_branches = true;
  1643. pt->branches_sample_type = attr.sample_type;
  1644. pt->branches_id = id;
  1645. }
  1646. pt->synth_needs_swap = evsel->needs_swap;
  1647. return 0;
  1648. }
  1649. static struct perf_evsel *intel_pt_find_sched_switch(struct perf_evlist *evlist)
  1650. {
  1651. struct perf_evsel *evsel;
  1652. evlist__for_each_reverse(evlist, evsel) {
  1653. const char *name = perf_evsel__name(evsel);
  1654. if (!strcmp(name, "sched:sched_switch"))
  1655. return evsel;
  1656. }
  1657. return NULL;
  1658. }
  1659. static bool intel_pt_find_switch(struct perf_evlist *evlist)
  1660. {
  1661. struct perf_evsel *evsel;
  1662. evlist__for_each(evlist, evsel) {
  1663. if (evsel->attr.context_switch)
  1664. return true;
  1665. }
  1666. return false;
  1667. }
  1668. static int intel_pt_perf_config(const char *var, const char *value, void *data)
  1669. {
  1670. struct intel_pt *pt = data;
  1671. if (!strcmp(var, "intel-pt.mispred-all"))
  1672. pt->mispred_all = perf_config_bool(var, value);
  1673. return 0;
  1674. }
  1675. static const char * const intel_pt_info_fmts[] = {
  1676. [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n",
  1677. [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n",
  1678. [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n",
  1679. [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n",
  1680. [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n",
  1681. [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n",
  1682. [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n",
  1683. [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n",
  1684. [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n",
  1685. [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n",
  1686. [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n",
  1687. [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n",
  1688. [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n",
  1689. [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n",
  1690. };
  1691. static void intel_pt_print_info(u64 *arr, int start, int finish)
  1692. {
  1693. int i;
  1694. if (!dump_trace)
  1695. return;
  1696. for (i = start; i <= finish; i++)
  1697. fprintf(stdout, intel_pt_info_fmts[i], arr[i]);
  1698. }
  1699. int intel_pt_process_auxtrace_info(union perf_event *event,
  1700. struct perf_session *session)
  1701. {
  1702. struct auxtrace_info_event *auxtrace_info = &event->auxtrace_info;
  1703. size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS;
  1704. struct intel_pt *pt;
  1705. int err;
  1706. if (auxtrace_info->header.size < sizeof(struct auxtrace_info_event) +
  1707. min_sz)
  1708. return -EINVAL;
  1709. pt = zalloc(sizeof(struct intel_pt));
  1710. if (!pt)
  1711. return -ENOMEM;
  1712. perf_config(intel_pt_perf_config, pt);
  1713. err = auxtrace_queues__init(&pt->queues);
  1714. if (err)
  1715. goto err_free;
  1716. intel_pt_log_set_name(INTEL_PT_PMU_NAME);
  1717. pt->session = session;
  1718. pt->machine = &session->machines.host; /* No kvm support */
  1719. pt->auxtrace_type = auxtrace_info->type;
  1720. pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE];
  1721. pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT];
  1722. pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT];
  1723. pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO];
  1724. pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO];
  1725. pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT];
  1726. pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT];
  1727. pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH];
  1728. pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE];
  1729. pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS];
  1730. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE,
  1731. INTEL_PT_PER_CPU_MMAPS);
  1732. if (auxtrace_info->header.size >= sizeof(struct auxtrace_info_event) +
  1733. (sizeof(u64) * INTEL_PT_CYC_BIT)) {
  1734. pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT];
  1735. pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS];
  1736. pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N];
  1737. pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D];
  1738. pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT];
  1739. intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT,
  1740. INTEL_PT_CYC_BIT);
  1741. }
  1742. pt->timeless_decoding = intel_pt_timeless_decoding(pt);
  1743. pt->have_tsc = intel_pt_have_tsc(pt);
  1744. pt->sampling_mode = false;
  1745. pt->est_tsc = !pt->timeless_decoding;
  1746. pt->unknown_thread = thread__new(999999999, 999999999);
  1747. if (!pt->unknown_thread) {
  1748. err = -ENOMEM;
  1749. goto err_free_queues;
  1750. }
  1751. err = thread__set_comm(pt->unknown_thread, "unknown", 0);
  1752. if (err)
  1753. goto err_delete_thread;
  1754. if (thread__init_map_groups(pt->unknown_thread, pt->machine)) {
  1755. err = -ENOMEM;
  1756. goto err_delete_thread;
  1757. }
  1758. pt->auxtrace.process_event = intel_pt_process_event;
  1759. pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event;
  1760. pt->auxtrace.flush_events = intel_pt_flush;
  1761. pt->auxtrace.free_events = intel_pt_free_events;
  1762. pt->auxtrace.free = intel_pt_free;
  1763. session->auxtrace = &pt->auxtrace;
  1764. if (dump_trace)
  1765. return 0;
  1766. if (pt->have_sched_switch == 1) {
  1767. pt->switch_evsel = intel_pt_find_sched_switch(session->evlist);
  1768. if (!pt->switch_evsel) {
  1769. pr_err("%s: missing sched_switch event\n", __func__);
  1770. goto err_delete_thread;
  1771. }
  1772. } else if (pt->have_sched_switch == 2 &&
  1773. !intel_pt_find_switch(session->evlist)) {
  1774. pr_err("%s: missing context_switch attribute flag\n", __func__);
  1775. goto err_delete_thread;
  1776. }
  1777. if (session->itrace_synth_opts && session->itrace_synth_opts->set) {
  1778. pt->synth_opts = *session->itrace_synth_opts;
  1779. } else {
  1780. itrace_synth_opts__set_default(&pt->synth_opts);
  1781. if (use_browser != -1) {
  1782. pt->synth_opts.branches = false;
  1783. pt->synth_opts.callchain = true;
  1784. }
  1785. }
  1786. if (pt->synth_opts.log)
  1787. intel_pt_log_enable();
  1788. /* Maximum non-turbo ratio is TSC freq / 100 MHz */
  1789. if (pt->tc.time_mult) {
  1790. u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000);
  1791. pt->max_non_turbo_ratio = (tsc_freq + 50000000) / 100000000;
  1792. intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq);
  1793. intel_pt_log("Maximum non-turbo ratio %u\n",
  1794. pt->max_non_turbo_ratio);
  1795. }
  1796. if (pt->synth_opts.calls)
  1797. pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC |
  1798. PERF_IP_FLAG_TRACE_END;
  1799. if (pt->synth_opts.returns)
  1800. pt->branches_filter |= PERF_IP_FLAG_RETURN |
  1801. PERF_IP_FLAG_TRACE_BEGIN;
  1802. if (pt->synth_opts.callchain && !symbol_conf.use_callchain) {
  1803. symbol_conf.use_callchain = true;
  1804. if (callchain_register_param(&callchain_param) < 0) {
  1805. symbol_conf.use_callchain = false;
  1806. pt->synth_opts.callchain = false;
  1807. }
  1808. }
  1809. err = intel_pt_synth_events(pt, session);
  1810. if (err)
  1811. goto err_delete_thread;
  1812. err = auxtrace_queues__process_index(&pt->queues, session);
  1813. if (err)
  1814. goto err_delete_thread;
  1815. if (pt->queues.populated)
  1816. pt->data_queued = true;
  1817. if (pt->timeless_decoding)
  1818. pr_debug2("Intel PT decoding without timestamps\n");
  1819. return 0;
  1820. err_delete_thread:
  1821. thread__delete(pt->unknown_thread);
  1822. err_free_queues:
  1823. intel_pt_log_disable();
  1824. auxtrace_queues__free(&pt->queues);
  1825. session->auxtrace = NULL;
  1826. err_free:
  1827. free(pt);
  1828. return err;
  1829. }